Superconducting Technology Assessment - nitrd

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1.5.1 FUNDING Three Funding Scenarios The development of RSFQ will vary depending on the level of available federal funding. Three possibilities were considered: aggressive government funding, moderate government funding, and a scenario devoid of any additional government investment. Level of Funding Aggressive Government Funding. Moderate Government Funding. No Additional Investment. 1.6 TECHNICAL ISSUES TABLE 1-2. THREE FUNDING SCENARIOS Expected Results The roadmaps presented assume aggressive government funding. This scenario presumes a sharing of the costs of development between government and industry, which the panel does not believe is a realistic expectation. With reduced government funding and without industrial contribution, the panel sees the technologies maturing much more slowly. This scenario leaves the entire development to industry. In this case, it is unlikely that the core SCE technology would mature sufficiently to build a machine in the foreseeable future. The panel would expect continued low-level investment in system architecture and programming environments, but no focused effort. 1.6.1 SUPERCOMPUTING SYSTEM CONSTRAINTS ON THE USE OF RSFQ While the goal of this study is not to develop a supercomputer system architecture, architectural constraints and opportunities are important for understanding how superconducting electronics technology would be deployed in a large system and what functionality would be demanded of the superconducting electronics. The earlier Hybrid <strong>Technology</strong> Multi-Threaded (HTMT) project provided a basis for understanding possible architectures using RSFQ electronics. Appendix F: System Architectures expands on the discussion below. (The full text of this appendix can be found on the CD accompanying this report.) 13
Structurally, a high-end computer will have a cryogenic core to house the RSFQ processors, including a communications fabric linking the RSFQ processing elements; surrounding this will be “staging” electronics connecting the core to a high-bandwidth, low-latency (optical) network; the network will connect to room temperature bulk memory and storage devices. The rationale is that: 14 CRYOGENIC ENVIRONMENT STAGING ENVIRONMENT ROOM TEMPERATURE ENVIRONMENT CMOS P/M Figure 1-3. Conceptual architecture. High-speed network for RSFQ inter-processor communications RSFQ P/M Staging electronics CMOS P/M Interprocessor network for data-intensive operations CMOS P/M RSFQ P/M Staging electronics CMOS P/M CMOS P/M CMOS P/M CMOS P/M ■ The superconducting processors provide very-high-speed computation, but memory capacity at 4 K is presently limited by low-density. This means that data must be swapped in and out, requiring communications between superconducting processing elements and the outside world to be as fast as possible. ■ The staging electronics will orchestrate the movement of data and instructions to and from the RSFQ processors, minimizing stale data in the critical high-speed memory resource. Communication to main memory will need a high-bandwidth network to support large-scale data movements and to provide a way to “gather” dispersed data from main memory into the staging electronics. The key system constraint is the availability and use of cryogenic memory. RSFQ P/M Staging electronics CMOS P/M RSFQ P/M Staging electronics CMOS P/M * P/M: Processor Memory
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25: The end point of this roadmap defin
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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