Superconducting Technology Assessment - nitrd

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Circuits/ Organizations Flux-1/ NG, Stony Brook U., JPL CORE 1_10/ ISTEC-SRL, Nagoya U., Yokohama National U. NG HYPRES HYPRES NG NSA, NG NG NG NG TABLE 3.1-1. PUBLISHED SUPERCONDUCTIVE CIRCUITS Function Complexity Speed Cell Library 8-bit microprocessor prototype 25 30-bit dual-op instructions 8-bit bit-serial prototype microprocessor 7 8-bit instructions 2.3 mW dissipation MAC and Prefilter for programmable pass-band ADC A/D converter Digital receiver FIFO buffer memory X-bar switch SFQ X-bar switch Chip-to-chip DFQ Driver/Receiver Current recycling 63K JJ 10.3x10.6 mm 2 7K JJ 3.4x3.2mm 2 6K - 11K JJ 5x5mm 2 6KJJ 12 K JJ 4K bit/ 2.6x2.5mm 2 32x32 module 32x32 module
Embedded Vector Registers, FIFO, and SFQ RAM In addition to logic, processor chips incorporate local memory. This is frequently in the form of registers and first-in, first-out registers (FIFOs). Small, embedded SFQ RAM is also useful. FIFOs can load and unload data using separate clocks that may be incoherent and are therefore useful as register memory and for resynchronizing data for two circuits running with slightly asynchronous clocks. Northrop Grumman tested a 32-bit RSFQ FIFO at 40 GHz, nearly as fast as the planned 50 GHz processor operation. The FIFO was made in the Northrop Grumman 4 kA/cm 2 process, where a 4 k FIFO (64 64-bit words) occupies a 5-mm square chip. Initial fabrication improvements, discussed in Chapter 4, will increase J C to 20 kA/cm 2 , quadrupling the size to 16 kbits (256, 64-bit words). Reducing metal line pitch and adding more superconducting wiring levels will further increase the density. The measured bias margins of the 32-bit FIFO measured at 40 GHz were ±17%, compared with ± 23% at low speed. Increasing the current density should increase the margins at high speed. A register file was developed by HYPRES based on a three-port memory cell with one input port and two independent output ports. Two different versions of this cell were demonstrated and patented. Such designs could produce multi-port registers. Small SFQ memory arrays are used today. Small RAM can more easily approach the clock speed and size required for inclusion on processor chips than large RAM blocks. Inter-chip Communications Both active and passive superconducting transmission lines have been used to transmit SFQ data over significant distances on-chip. The active lines are a series of Josephson SFQ repeaters called a Josephson transmission line (JTL). Passive transmission lines (PTL) can propagate SFQ pulses on microstrip or striplines at >60 Gbps. The latter technique is preferred, because it uses less power and produces less jitter. Passive transmission line communication was used extensively on the Flux-1 chip. The velocity in superconducting transmission lines is about 1/3 the free space velocity, 0.1 mm/ps. Time-of-flight (TOF) in JTLs is longer because of the switching delay at every junction. A more challenging problem is communication of SFQ data between chips on an MCM and, eventually, between PC boards. Communication between chips requires the SFQ pulses to traverse the discontinuities between the chip and the MCM. Transmission lines are matched to the junction impedance, typically 1-10 Ω. On-chip, these lines are several microns wide. The transmission lines on the MCM substrate are much wider, because the dielectric insulation layers are significantly thicker on the MCM. In addition to this geometric discontinuity, the signal and ground solder bumps introduce parasitic inductance and capacitance. Until 2002, conventional wisdom held that SFQ pulses could not be transmitted through a passive substrate; researchers in Japan demonstrated that SFQ pulses could be transmitted through an “active” substrate. However, Northrop Grumman developed a unique, efficient, high-speed driver-receiver for inter-chip communications through solder-bumps on an MCM and demonstrated low bit-error-rate to 60 GHz. In addition to special communication circuits, it was necessary to tailor the local bump configuration to tune out the parasitics. This required both analog simulations and iterative experimental tests. The location and distribution of ground bumps and contacts is of equal importance as the signal line. A ground bump introduces inductance not only by the bump geometry, but also by its distance from the signal bump. Ideally, the ground bump would be coaxial with the signal to simulate a coaxial line. Since this is not feasible, Flux-1 used four ground bumps surrounding the signal at minimum separation (Figure 3.1-3). Since many high-speed lines are required, it was necessary to share ground bumps. Simulations showed that cross-talk at the ground bumps was negligible. 46
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: Structurally, a high-end computer w
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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