Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
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MRAM Future Projections<br />
MRAM is a very attractive RAM option with a potentially high payoff. Compared to SFQ RAM, MRAM is<br />
non-volatile, non-destructive readout, and higher density, albeit slower. Compared to hybrid JJ-CMOS, monolithic<br />
RSFQ-MRAM does not require signal amplification to convert mV-level SFQ input signals to CMOS operating voltage,<br />
which should improve relative access and cycle times. If 50psec SMT switching is achieved, memory cycle times<br />
should be between 100 and 200ps. A 200ps cycle time MRAM—where RSFQ-based floating point units and vector<br />
registers are communicating with multiple 64-bit wide memory chips—translates to a local memory bandwidth of<br />
~40GBytes/s. Thus, cryogenic superconducting-MRAM could well meet the minimum local memory bandwidth<br />
requirement of ~2 Bytes/FLOP for a 200-GFLOP processor.<br />
High-density, stand-alone superconducting-MRAM main memory—even with 500 ps to 1 ns cycle times—could be<br />
a big win since this would allow the entire computer to be contained within a very small volume inside the cryostat,<br />
reducing the communication latency to a bare minimum in comparison with external main memory. Such an<br />
arrangement would expose the entire MRAM memory bandwidth to the RSFQ logic, providing RSFQ processor<br />
arrays access to both extremely fast local as well as global main memory. Superconductive-MRAM mass memory<br />
should also dissipate less power than RT CMOS, since all high-speed communication would be confined to the cryostat.<br />
RSFQ MRAM density should be able to track that of commercial MRAM with some time lag. Monolithic 4 Mb<br />
RSFQ-MRAM chips operating at 20 GHz would provide the low-latency RAM needed for 100 GHz RSFQ processors.<br />
It will, however, require investment beyond 2010 to bring this high-payoff component to completion.<br />
Understanding and optimizing the cryogenic performance of MRAM technology is important. Fortunately, device<br />
physics works in our favor.<br />
64<br />
■ MRAM has a higher MR at low temperatures due to reduced thermal depolarization<br />
of the tunneling electrons. A 50% increase in MR from room temperature to 4 K is typical.<br />
Higher MR combined with the lower noise inherent at cryogenic operation provides faster<br />
read than at room temperature and lower read/write currents.<br />
■ Since thermally induced magnetic fluctuations will also decrease at low temperatures,<br />
the volume of magnetization to be switched can be reduced, with a concomitant reduction<br />
in switching current and power dissipation.<br />
■ Resistive metallization, such as Cu used in commercial MRAM chips, can be replaced with<br />
loss-less superconducting wiring. This will dramatically reduce drive voltages and total<br />
power dissipation, since ohmic losses are at least an order-of-magnitude higher than the<br />
dynamic power required to switch the bits. Calculations indicate that the field energy per pulse<br />
approximates 60 fJ per mm of conductor, or 240 fJ to write a 64-bit word. Without ohmic<br />
losses, the energy required to write a FS-MRAM at 20 GHz is simply 240 fJ times 20 GHz,<br />
or 5 mW at room temperature. Reading would require approximately one-third the power<br />
or ~1.7 mW. For SMT with 50 ps switching, power per bit reduces to ~10 fJ. If switching currents<br />
can be further reduced below 1 mA, as expected at low temperatures, the dynamic power<br />
dissipation in the memory would go down even further. A more accurate assessment of total<br />
power dissipated in the memory depends on memory arrangement and parasitic loss mechanisms.