Superconducting Technology Assessment - nitrd

Speed and Density
The first planned product from Freescale Semiconductor is very similar to their 4Mb Toggle MRAM demonstration
circuit, which had a 1.55-µm 2 cell size in a 0.18 µm CMOS process. This circuit had symmetric read and write cycle
times of 25 ns. The Freescale circuit was designed as a general-purpose memory, but alternate architectures can be
defined to optimize for lower power, higher speed, or higher density. Each optimization involves engineering tradeoffs
that require compromise of the less-important attributes. For example, a two-MTJ cell can be used
to provide a larger signal for much higher speeds, but it will occupy nearly double the area per cell. A 128 kb
high-speed circuit with 6-ns access time has recently been demonstrated by IBM. Since much of the raw signal
(resistance change) is consumed by parametric distributions and process variations, relatively small increases in MR
will result in large improvements in read speed. MTJ materials with four times higher MR have recently been
demonstrated. It is therefore reasonable to expect continued improvements in access time especially at cryogenic
temperatures where bit-to-bit fluctuations are dramatically reduced. Table 1 compares the performance of several
memory technologies at the 90-nm IC node at room temperature, including that for a general-purpose MRAM
and a high-speed MRAM. (Stand-alone 90-nm CMOS memory is in production today, although the embedded
configuration is yet to be released.) Note that DRAM and Flash cell sizes are dramatically larger when embedded,
as compared to the stand-alone versions. On the other hand, due to their backend integration approach, MRAM
cell sizes remain the same for embedded and stand-alone.
Table 1. Comparison of MRAM with semiconductor memories. The MRAM column represents a general-purpose
memory, while the High-Speed MRAM column represents architectures that trade some density for more speed.
Either type of MRAM can be embedded or stand alone. Stand-alone Flash and DRAM processes become more
specialized in order to achieve high density, and have much lower density when embedded, due to differences in
fabrication processes compared to the underlying logic process. The density and cell size ranges for these two
latter memories are very large due to the compromise needed for embedded fabrication.
Technology
Node
*marks the embedded end of the range.
180
MRAM MRAM
0.18 µm
Demo
90 nm
Target
High-
Speed
MRAM
90 nm
Target
FLASH SRAM DRAM
90 nm
Typical
90 nm
Typical
90n m
Typical
Density (Mb) 1 - 32 16 - 256 4 - 32 4* - 4000 4 - 64 16* - 1,000
Wafer Size (mm) 200 200/300 200/300 200/300 200/300 200/300
Cycle Time (ns) 5 - 35 5 - 35 1 - 6
40-80 (Read)
~10 6 (Write)
0.5 - 5 6 - 50
Array Efficiency 40% - 60% 40% - 60% 40%-60% 25% - 40% 50% - 80% 40%
Voltage 3.3V/1.8V 2.5V/1.2V 2.5V/1.2V
2.5V/1.2V
9V - 12V
internal
2.5V/1.2V 2.5V/1.2V
Cell Size (um 2 ) 0.7 - 1.5 0.12 - 0.25 0.25 - 0.50 0.1 - 0.25* 1 - 1.3 0.065-0.25*
Endurance
(cycles)
>10 15
>10 15
>10 15
>1015 read,
10 15
Non-Volatile YES YES YES YES NO NO
>10 15