Superconducting Technology Assessment - nitrd

INTERCONNECTS AND SYSTEM
INPUT/OUTPUT
In petaflops-scale computer systems, the processor to memory and processor to processor data rates are enormous
by any measure. The hybrid technology multi-thread (HTMT) program estimated the bisectional bandwidth requirement
to be 32 petabits/s. This bandwidth is composed of communications from relatively distant secondary storage, lowlatency
communications with “nearby” primary storage, and communications between processor elements within
the cryogenic Rapid Single Flux Quantum (RSFQ) processing units.
The use of cryogenic RSFQ digital circuits with clock frequencies exceeding 50 GHz imposes challenges resulting
from the increasing differential between memory cycle time and processor clock. Reduced time-of-flight (TOF)
latency motivates the use of cryogenic memory close to the processor. Providing the required bandwidth between
room-temperature electronics and the cryogenic RSFQ processor elements requires careful engineering of the
balance between the thermal load on the cryogenics and the number, type, bandwidth, and active elements of the
lines providing input/output (I/O).
The major interconnection, data communication, and I/O needs of a petaflops-scale system based on cryogenic
RSFQ technology are:
■ High throughput data input to the cryogenic processors and/or memory at 4 K.
■ High throughput output from the 4 K operating regime to room-temperature system
elements such as secondary storage.
■ Communication between processor elements within the 4 K processing system at data
rates commensurate with the processor clock rate.
In order to minimize the line count (thereby minimizing thermal and assembly issues) yet provide the requisite capability
to carry tens of petabits/s of data, the bandwidth of each individual data line should be at least tens of Gbps.
Optical technologies offer a potential solution to this requirement while offering much lower thermal loads than
Radio Frequency (RF) electrical cabling. However, optical components need to overcome issues of power, cost,
and cryogenic operation. The low voltage levels of superconductive electronic devices are a challenge to direct
communication of RSFQ signals from 4 K to room temperature. Some combination of Josephson junction (JJ),
semiconductor, and optical components operating at a variety of temperatures will probably be required to provide
the combination of data rate, low line count, and low thermal load required.
In a hierarchical supercomputer, such as any RSFQ petaflops system is likely to be, processor performance can be
improved by data communication and manipulation at different levels of the memory hierarchy. As an example,
HTMT provided a great deal of data manipulation and communication at the room temperature level using an
innovative interconnection architecture called a Data Vortex. The Lightwave Research Laboratory at Columbia
University has recently demonstrated a fully implemented 12-port Data Vortex Optical Packet Switch network with
160Gbps port bandwidth yielding a nearly 2Tbit/sec capacity.
Another challenge is the low latency (ns range) requirement imposed for data movement within the thousands of
processors and memories at cryogenic temperature. Superconducting switches offer a potential solution for direct
interfacing between RSFQ based processors and their immediate memory access. Table 5-1 summarizes the
technologies, issues, and development for the data communication requirements of a cryogenic RSFQ petaflops-scale
system. The panel estimates that the roadmap for these elements will require $91.5 million (M), with a large team
working some parallel paths early, then focusing down to a smaller effort demonstrating capability required for
petaflops-scale computing by 2010.
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