Superconducting Technology Assessment - nitrd

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INTERCONNECTS AND SYSTEM INPUT/OUTPUT In petaflops-scale computer systems, the processor to memory and processor to processor data rates are enormous by any measure. The hybrid technology multi-thread (HTMT) program estimated the bisectional bandwidth requirement to be 32 petabits/s. This bandwidth is composed of communications from relatively distant secondary storage, lowlatency communications with “nearby” primary storage, and communications between processor elements within the cryogenic Rapid Single Flux Quantum (RSFQ) processing units. The use of cryogenic RSFQ digital circuits with clock frequencies exceeding 50 GHz imposes challenges resulting from the increasing differential between memory cycle time and processor clock. Reduced time-of-flight (TOF) latency motivates the use of cryogenic memory close to the processor. Providing the required bandwidth between room-temperature electronics and the cryogenic RSFQ processor elements requires careful engineering of the balance between the thermal load on the cryogenics and the number, type, bandwidth, and active elements of the lines providing input/output (I/O). The major interconnection, data communication, and I/O needs of a petaflops-scale system based on cryogenic RSFQ technology are: ■ High throughput data input to the cryogenic processors and/or memory at 4 K. ■ High throughput output from the 4 K operating regime to room-temperature system elements such as secondary storage. ■ Communication between processor elements within the 4 K processing system at data rates commensurate with the processor clock rate. In order to minimize the line count (thereby minimizing thermal and assembly issues) yet provide the requisite capability to carry tens of petabits/s of data, the bandwidth of each individual data line should be at least tens of Gbps. Optical technologies offer a potential solution to this requirement while offering much lower thermal loads than Radio Frequency (RF) electrical cabling. However, optical components need to overcome issues of power, cost, and cryogenic operation. The low voltage levels of superconductive electronic devices are a challenge to direct communication of RSFQ signals from 4 K to room temperature. Some combination of Josephson junction (JJ), semiconductor, and optical components operating at a variety of temperatures will probably be required to provide the combination of data rate, low line count, and low thermal load required. In a hierarchical supercomputer, such as any RSFQ petaflops system is likely to be, processor performance can be improved by data communication and manipulation at different levels of the memory hierarchy. As an example, HTMT provided a great deal of data manipulation and communication at the room temperature level using an innovative interconnection architecture called a Data Vortex. The Lightwave Research Laboratory at Columbia University has recently demonstrated a fully implemented 12-port Data Vortex Optical Packet Switch network with 160Gbps port bandwidth yielding a nearly 2Tbit/sec capacity. Another challenge is the low latency (ns range) requirement imposed for data movement within the thousands of processors and memories at cryogenic temperature. Superconducting switches offer a potential solution for direct interfacing between RSFQ based processors and their immediate memory access. Table 5-1 summarizes the technologies, issues, and development for the data communication requirements of a cryogenic RSFQ petaflops-scale system. The panel estimates that the roadmap for these elements will require $91.5 million (M), with a large team working some parallel paths early, then focusing down to a smaller effort demonstrating capability required for petaflops-scale computing by 2010. 97
98 Data Communication Requirement Room Temperature to Cryogenic (Input) Cryogenic to Room Temperature (Output) Cryogenic to Cryogenic TABLE 5-1. I/O TECHNOLOGIES FOR PETAFLOPS-SCALE PROCESSING WITH RSFQ Technology Status Projections/Needs Direct Optical to RSFQ Optical with OE conversion at 40-77 K Direct Electrical input Direct RSFQ to Optical RSFQ to intermediate temperature electrical to optical out RSFQ Electrical Out Superconducting switch – 40-50 Gbps components available off the shelf, few demonstrations at cryo. – 20 Gbps RT to RSFQ demonstrated in the 90’s. – 40-50 Gbps components available off the shelf, no demonstrations at cryo. – Well understood from R&D and small-scale applications. – Cable technology restricts practical line rates to
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109: 05 Packaging and chip-to-chip inter
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ Construct a detailed supercondu
Page 151 and 152: Appendix B
Page 153 and 154: 140 George Cotter Nancy Welker Doc
Page 155 and 156: Appendix C
Page 157 and 158: 144 TERMS/DEFINITIONS IHEC Integrat
Page 159 and 160: Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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