Superconducting Technology Assessment - nitrd

B. Yield
Yield measurements are an important part of any manufacturing
process [95]. Several parts, including wafer fabrication
yield, parametric test yield, functional test yield, and packaging
yield factor in overall product yield. Of these, wafer
fabrication yield is the easiest to measure. Parametric test
yield is being addressed through the use of standard test vehicles
as described previously. Quantitative estimates of functional
test yield may be difficult because it requires enough
resources to test a large quantity of circuits of a given type
to establish reliable yield statistics. Ideally, measured circuit
yield can be correlated with parametric test yield and used
to project yield of more complex circuits [96]–[98]. Testing
at speed is also important because margins may be strong
functions of frequency over some range. Packaging yield is
important in the production of products or systems and will
become more important as the superconductor electronics
community fields more products based on active circuits.
Although parameter variations are known, little work
has been done in superconductor electronics in the area of
yield assessment. Since it is difficult to determine circuit
yield from measurements of discrete device components,
one would ideally develop a product-oriented yield vehicle
that will allow a better understanding of the process yield,
to correlate its yield with PCM measurements of spreads,
etc., and to predict yield on future products. Several yield
vehicles such as RAM [99] and shift registers [91], [98] have
been developed to provide this type of information.
In the absence of more extensive yield data, one can nevertheless
make projections about the effects of defect density
and its effect on die yield by leveraging the yield models
developed for the semiconductor industry. These models are
directly applicable to superconductor electronics because the
fabrication processes are similar. The relationship between
yield and defect density is based on the model
AD , where is the defect sensitive area, is defect
density, and describes how the defects tend to cluster on
the wafer [95]. For a given defect density, smaller area chips
will have a higher yield than larger area chips. Estimates for
present defect densities are 1 or 2 defects/cm and 0.5
(defects clustered toward the edges of the wafer). Based on
this model, it is clear that defect density is an important consideration
for high yield. NGST concluded, after a major effort
to reduce gross visual defects, that most defects were
induced by process tools and not by the fabrication facilities
that were already operating at class 10 or better. Further
reductions in defect density would require cleaner process
tools.
VI. PROCESS BENCHMARKING: STATIC DIVIDER
PERFORMANCE
The maximum operating speed of the toggle flip-flop
(TFF) has become the standard measure or benchmark used
to compare superconductor integrated circuit fabrication
processes [18], [100], [101]. The TFF also has been used
to compare the performance of semiconductor processes
Fig. 14. Maximum reported TFF divider speed � versus
t for trilayers from HYPRES, NGST, and SUNY. The numbers
adjacent the to NGST points indicate the optimum s ‚ product
of the shunted junctions used in the TFF. Also, shown is the
projected divider speed of $450 GHz for the next-generation
20-kA/cm process.
[102], but it is important to distinguish between true “static”
divide-by-two operation from narrow band operation, which
often results in inflated claims of switching speed. True static
divide-by-two operation means that a well-designed TFF
operates correctly from near dc to its maximum reported
frequency without adjusting its bias point. The near-dc frequency
response is necessary if the gate is to function with
arbitrary data which may have long strings of logical zeros or
ones. Superconductor integrated circuit fabrication process
benchmarks or maximum TFF speeds are based on the more
stringent measurements of static divider performance.
The NGST standard benchmark circuit is a 12-stage static
divider that consists of an on-chip voltage-controlled oscillator
(VCO) (a dc SQUID with damped junctions) and a 12-b
TFF counter chain. Each stage of the counter chain uses of
a symmetric four-junction TFF with symmetric current bias
and a separate magnetic flux bias, which is described elsewhere
[103]. The last two bits of the counter chain have
self-resetting junction outputs that can be counted by a room
temperature electronic frequency counter.
The circuit parameters are chosen to optimize operating
margin and yield at high speed. The design of the NGST
static divider uses junctions that are slightly underdamped. 1
The maximum divider speeds achieved are just above
200 and 300 GHz for the 4-kA/cm and 8-kA/cm processes,
respectively. These results along with results from
HYPRES and SUNY for other ’s are shown in Fig. 14.
The maximum divider speed scales approximately
as kA/cm GHz to about 50 kA/cm , above
which the speed saturates at a frequency corresponding to
the gap frequency for Nb. There is good agreement among
the different niobium trilayer processes shown in Fig. 14.
Details of the divider speed measurements and characterization
can be found in [18], [59].
1 For the 8-kA/cm process, s ‚ aIXHS mV for a Stuart–McCumber
parameter @ AaPXS and for 4-kA/cm Ys ‚ aHXU mV, and aPXH.
1528 PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004