Superconducting Technology Assessment - nitrd

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To maximize both the magnetic and radiation shielding in digital SCE systems, any gaps in the shields, such as those required to feed in I/O cables, need to be minimized. A significant benefit of flexible ribbon cables are their ~0.1" bending radius and
These properties enable the possibility of making flexible MgB 2 thin-film leads for high-speed signal propagation. The next step in a development effort could include demonstration of MgB 2 film growth on suitable flexible substrate tapes of the size discussed above. By making the tape from Si 3N 4 over an etched away grid of Si screening, the thermal contribution of the supporting tape could be minimized. Alternatively, growth on single-crystal YSZ and polycrystalline alumina substrates without the use of a buffer layer have already been achieved. Thus growth on flexible YSZ tape may be straightforward. Growth on other materials with suitable high-frequency properties (such as the flexible “RT/duroid”) should also be investigated. The two sided growth allows a strip line geometry with the substrate as the dielectric to be realized, but work on deposited dielectrics is desirable to minimize signal cross talk and increase signal trace density. It is estimated that such tapes could be productized within four years if an engineering development program is implemented. The effects of the current recycling on the high frequency operation of SCE circuits require further development and testing. The operation at 50 GHz and beyond with acceptable bit-error-rates (BER) needs further development and testing, including physical issues (e.g., conductive and dielectric material selection, dielectric losses) and electrical issues (signaling types, drivers and receivers). The combination of good electrical and poor thermal conductance is inherently difficult to meet since a good electrical conductor is also a good thermal conductor. Specialized coaxial cables have been commonly used for multi-GHz I/O connections and can support operation up to 100 GHz. These cables employ relatively low thermal conductivity materials such as silver-plated steel and beryllium-copper, and can have diameters down to 20 mils. However, hand-wired coax is not practical for systems that require thousands or millions of I/O lines. The required density of I/O lines in large scale systems is a factor of 10 greater than the density achievable today (0.17 lines/mil) for flexible ribbon cables. One method to increase the apparent density of the cables is to piggy back or stack several flex cables, but this does lead to increased complexity and may limit the MCM-to-MCM spacing. Optical interconnects may requires the use of elements such as prisms or gratings. These elements can be relatively large, and may not fit within the planned size of the cryostat. The power required for the optical receivers, or the thermal energy delivered by the photons themselves may offset any gains from using the low thermal conductance glass fibers. A detailed design is needed to establish these trade-offs. The use of HTS wires includes two significant technical risks: ■ Currently, the best HTS films are deposited epitaxially onto substrates such as lanthanum-aluminate or magnesium oxide. These substrates are brittle and have relatively large thermal conductance which offset the “zero” thermal conductivity of the HTS conductors. ■ Any HTS cable would need to have at least two superconductor layers (a ground plane and a signal line layer) in order to carry multi-Gbps data. Presently, multilayer HTS circuits can only be made on a relatively small scale due to pin-holes and other such defects which short circuit the two layers together. 242
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
Page 203 and 204: Fig. 4. Junction fabrication proces
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: Fig. 11. Ground plane planarization
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: Fig. 17. Photograph of the FLUX-1r1
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
Page 215 and 216: Appendix J
Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
Page 223 and 224: Fig. 8. Layout-versus-Schematic ver
Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
Page 239 and 240: Appendix L
Page 241 and 242: The bandwidth, chip density and int
Page 243 and 244: While using short flex cables is th
Page 245 and 246: We must note that the reparability
Page 247 and 248: Figure 7. A typical cryocooler encl
Page 249 and 250: Small Cryocoolers Among commercial
Page 251 and 252: Although cooling of the 4 K circuit
Page 253: Supplying DC current to all of the
Page 257: For additional copies, please conta
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