Superconducting Technology Assessment - nitrd

Figure 6.3. A multi-chip module with SCE chips( left: NGST ‘s Switch chip MCM with amplifier chip, center: NGST’s MCM; right HYPRES’ MCM).
6.1.2 MULTI-CHIP MODULES AND BOARDS – READINESS
The design of MCMs for SCE chips is technically feasible and fairly well understood. However, the design for higher
speeds and interface issues needs further development. The panel expects that MCMs for processor elements of a
petaflops-scale system will be much more complex, requiring many layers of impedance controlled wiring, with
stringent crosstalk and ground-bounce requirements. While some of the MCM interconnection can be accomplished
with copper or other normal metal layers, some of the layers will have to be superconducting in order to maintain
low bit error rate (BER) at 50 GHz for the low voltage RSFQ signals. Kyocera has produced limited numbers of such
MCMs for a crossbar switch prototype. These MCMs provide an example and base upon which to develop a suitable
volume production capability for MCMs.
At intermediate temperatures, complex boards (some with embedded passive components) have been evaluated and
tested for low-temperature operation. Although MCMs with SCE chips are feasible, the signal interface and data links
impose further challenges. In particular, the large number of signal channels and high channel densities are difficult to achieve.
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