Superconducting Technology Assessment - nitrd

Cryogenic CMOS memory is also a candidate for 40 K application as a second-level RAM. A key advantage is that
the CMOS memory cells do not leak at 40 K, which means that compact 3-transistor DRAM-type memory cells can
be used as SRAM without the overhead of refreshing that is necessary at room-temperature. It is therefore possible
to make very compact, high-capacity memory located at the 40 K stage as a back-up for 4 K RAM. The memory
chip design will require close collaboration between the architecture and memory design teams in the first year of the
project in order to find the best techniques for processor-memory communication and RAM chip internal organization
to meet the read/write latency, access cycle time, and bandwidth requirements of 50 GHz processors.
Hybrid JJ-CMOS RAM Issues and Concerns
The measurements to date on the hybrid Josephson-CMOS memory have all been done at low speed. It is possible that
some unexpected issues relating to the frozen-out substrate in the CMOS could cause difficulty in high-speed operation.
Hybrid JJ-CMOS RAM Roadmap
Hybrid JJ-CMOS RAM Investment
The $14.2 million (M) total investment required for hybrid JJ-CMOS RAM detailed above is based principally on a
hybrid JJ-CMOS team of about 8 persons for five years plus the cost of fabricating 180-nm CMOS chips and 90-nm
CMOS wafers. Part of the initial effort could be carried out in a university in parallel with the main industrial effort.
This effort would also be able to evaluate CMOS RAM for the second-level memory. The JJ foundry costs are included
in the foundry budget.
3.2.2 MEMORY – SINGLE-FLUX-QUANTUM MEMORY
SFQ RAM is a completely superconductive memory, including decoders, drivers, cells, and readout. The ideas are
compatible with RSFQ logic and employ that logic for the decoders and detectors.
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Test 64-kb bit-slice, optimize design
Develop embedded-chip packaging
Fabricate embedded JJ-CMOS chips
Design and test 64 kb RAM
TABLE 3.2-3. HYBRID JJ-CMOS RAM ROADMAP
Develop 256 kb RAM, measure access- and cycle-time
Develop new CMOS decoder and input interface
Fabricate JJ circuits on whole wafer 90 nm CMOS RAM wafers
Demonstrate 64 kb and 256 kb RAM chips
Fabricate JJ circuits on redesigned 90 nm CMOS RAM wafers
Develop processor-memory communication
Complete the processor-memory package, test and evaluate
Total Investment
Milestone Year Cost ($M)
2006
2006
2006
2007
2007
2008
2008
2008
2009
2009
2010
2.4
2.4
3.5
3.5
2.4
14.2