Superconducting Technology Assessment - nitrd

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INTRODUCTION TO SUPERCONDUCTOR SINGLE FLUX QUANTUM CIRCUITRY The Josephson junction (JJ) is the intrinsic switching device in superconductor electronics. Structurally a JJ is a thin-film sandwich of two superconducting films separated by a very thin, non-superconducting, barrier material. For the junctions of interest here, the superconductors are Nb and the barrier material is a dielectric, aluminum oxide. The barrier is sufficiently thin, ~1nm, that both normal electrons and superconducting electron pairs can tunnel through the barrier. Electrically, a tunnel junction between normal metals is equivalent to an ohmic resistor shunted by a capacitor. If the metals are superconductors, however, electron pairs can tunnel at the same rate as normal electrons. Only pairs can tunnel at zero voltage, while both pairs and normal electrons tunnel if a voltage appears across the junction. Pair tunneling gives rise to a third parallel channel, resulting in unique electrodynamics and highly-nonlinear current-voltage characteristics. I c R d Current Figure 1. Equivalent circuit of Josephson junctions. I C represents the nonlinear switch. JJs are characterized by the equivalent circuit shown in Figure 1, where I C is the critical current (maximum current at zero voltage) of the junction, C is the capacitance, and R d is the resistance. C is capacitance of the junction. R d is the parallel combination of the internal junction resistance and any external shunt. Low-inductance shunts are commonly employed in RSFQ circuits to control junction properties. The intrinsic junction resistance is very voltage dependent as shown in Figure 2a. It is very large compared with typical external shunts for voltages below the energy gap, V g ~2.7 mV for niobium (Nb), and very small at the gap voltage. Above the gap voltage, the resistance becomes ohmic, with a value R N, the resistance of the junction in the non-superconducting state. The product I CR N is approximately V g. C � Voltage � 147
The time-dependent behavior of this equivalent circuit is given by summing the three current components illustrated in Figure 1, resulting in a non-linear differential equation, (1) The first term represents a parametric Josephson inductance whose value scales as L J = Φ 0/2πI C. Damping is controlled by the parameter β C =R 2 C/L J, the ratio of the junction time constants RC and L J/R. In digital circuits, JJs operate in two different modes: voltage-state (latching) and single flux quantum (non-latching). Figure 2 illustrates the static current-voltage characteristics of these two device modes, which are also characterized as under-damped and over-damped, respectively. JJs are always current-driven at zero-voltage, so their behavior depends on their response to the external current. In Figure 2a, the I-V characteristics are multi-valued and hysteretic, such that the junction switches from V = 0 to V g at I = I C. If the current is reduced near zero, the junction resets in the zero-voltage state. This provides a two-state logic voltage that was the basis of the IBM and Japanese computing projects in the 1970’s and 1980’s. If the junction is shunted by a small resistor, the I-V characteristic is single-valued as shown in Figure 2b. The voltage can increase continuously from zero as the current increases above I C. I(mA) The early work exemplified by the IBM and the Japanese Josephson computer projects exclusively used voltagestate logic, where the junction switching is hysteretic from the zero-voltage to the voltage state. This necessitated an AC power system in order to reset the junction into the zero-voltage state. The speed of this technology was limited to about 1 GHz. 148 0.2 0.1 Underdamped Junction ------------------------- V (mV) I (mA) 0.0 0.0 0 2 4 0 Figure 2a. DC electrical characteristics of voltage-state latching junctions 0.2 Overdamped Junction 0.1 ----------------------------- Ic � V (mV) Figure 2b. DC electrical characteristics of SFQ non-latching junctions 1
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ Construct a detailed supercondu
Page 151 and 152: Appendix B
Page 153 and 154: 140 George Cotter Nancy Welker Doc
Page 155 and 156: Appendix C
Page 157 and 158: 144 TERMS/DEFINITIONS IHEC Integrat
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Page 163 and 164: RSFQ electronics is faster and diss
Page 165 and 166: Similar to CMOS, the irreducible po
Page 167 and 168: Appendix E
Page 169 and 170: The report further identified four
Page 171 and 172: Analog high temperature superconduc
Page 173 and 174: Appendix F
Page 175 and 176: Only one significant effort to arch
Page 177 and 178: Execution Models Organizing hardwar
Page 179 and 180: Development Issues and Approaches T
Page 181 and 182: Appendix G
Page 183 and 184: The two-junction comparator, the ba
Page 185 and 186: Bias Currents A major cause of degr
Page 187 and 188: Power and bias current Power is dis
Page 189 and 190: Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 0.08 0.06 0.04 0.02 30 40 50 60 70
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Fig. 4. Junction fabrication proces
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: Fig. 11. Ground plane planarization
Page 209 and 210: B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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