Superconducting Technology Assessment - nitrd

The superconductive IC chip fabrication process will build upon existing experience and concepts that already have
been proposed or demonstrated in superconductive circuits. Figure 4-4 is a cross-sectional view of a conceptual
superconductive IC chip process corresponding to 2009 in Table 4-5. It relies extensively on metal and oxide
chemical-mechanical planarization (CMP). This process has one ground plane, four wiring layers (including base
electrode), two resistor layers, self-aligned junction contacts, and vertical plugs or pillars for interconnection vias
between wiring layers. The aspect ratio of the vertical plugs is on the order of 1:1, which does not require the
complex chemical vapor deposition or hot metal deposition processes typically used in semiconductor fabrication
to fill vias of more extreme aspect ratio. Power lines and biasing resistors are located below the ground plane to
isolate the junctions from the effect of magnetic fields and to increase circuit density. The final superconductive IC
chip process is likely to include an additional wiring layer and/or ground plane and vertical resistors to reduce the
chip real estate occupied by junction shunt resistors.
Superconductive IC chip fabrication for petaflops-scale computing far exceeds the capability of existing superconductive
foundries, even the former NGST foundry. However, the required level of integration has been available for several years
in the semiconductor industry. Comparison with the Semiconductor Industry Association (SIA) roadmap suggests that
a Nb superconductive process implemented in 1995 CMOS technology would be adequate. The fabrication tools,
including advanced lithography, CMP, and infrastructure support, are readily available, so no major new technologies
or tools are required to produce the superconductive IC chips needed for petaflops-scale computing.
4.5 IC CHIP MANUFACTURE – ISSUES AND CONCERNS
RSFQ logic offers an extremely attractive high-speed and low-power computing solution. Low power is important,
because it enables both high IC chip packaging density and low-latency interconnects. For large systems, total
power is low despite the penalty associated with cooling to cryogenic temperatures.
The major issues relevant to the circuit complexity, speed, and low power necessary for petaflops-scale computing
are discussed below.
4.5.1 IC CHIP MANUFACTURE – IC MANUFACTURABILITY
In section 4.3, the panel listed the technical challenges involved in the fabrication of ICs suitable for petaflops-scale
computing. SCE technology will have to improve in at least three key areas including reduction in feature size,
increase in layer count, and increase in gate density. While the required level of complexity is commonplace in
high-volume semiconductor fabrication plants, it represents a significant challenge, particularly in terms of yield
and throughput.
Scaling to petaflops requires more than a 10-fold increase
in circuit density along with a decrease in feature sizes to several
times smaller than present day technology.
At present, Nb-based JJ technology is at the 10 4 -10 5 JJ/cm 2 integration level, with minimum feature sizes of ~1
µm, depending on the foundry. Although the technology can support up to 10 5 JJ/cm 2 , circuits of this scale have
not been demonstrated due to other yield-limiting factors. Scaling to petaflops requires more than a 10-fold
increase in circuit density to at least 10 6 JJ/cm 2 , along with a decrease in feature sizes to several times smaller than
present day technology (to 0.5 - 0.8 µm for junctions and ~0.25 µm for minimum features), as shown in the
technology roadmap (Table 4-5). Additional superconducting interconnect layers are also required.
84