Superconducting Technology Assessment - nitrd

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Issues and Concerns Present simulation, layout, and verification tools could form the foundation of a new CAD capability. Translating existing CAD capability, DRC, LVS, and generation of Pcells for physical layout, to a new foundry process or processes should be quick and relatively easy. Additional CAD development should be driven by advances in feature size, signal frequency, integration scale, and circuit complexity, all of which need to leapfrog present capability by several generations. Physical models A mature RSFQ technology will operate closer to ultimate physical limits than present technology. Ultimately, this will require new models of junctions, quantum noise, transmission lines, and inductors for physical simulation. Points for consideration include: ■ JJs. The present RSJ model may not be adequate for sub-micron, high J C junctions. ■ Quantum noise. Quantum noise may add significantly to thermal noise in high J C junctions. ■ Transmission lines. These are presently considered dispersion- and attenuation-free, which may not be adequate for signals with frequency content approaching the Nb gap frequency (about 800 GHz). ■ Inductors. Kinetic inductance becomes increasingly large relative to magnetic inductance at sub-micron linewidths and may be frequency dependent at high frequency. All of these effects should be manageable if they can be captured in physical simulation. Standard physical simulators have already been extended to include superconductive elements such as JJs (e.g., WRSpice). Addition of new elements may now be required. Parameter extraction from physical layout is needed both for LVS and for back annotation, whereby a netlist is generated from the physical layout. Verification is presently done without checking inductance values. Back annotation presently can only be done at the gate level using LMeter. A true 3D EM (3-dimensional electromagnetic) algorithm may be required to attain high accuracy at sub-micron sizes. Both the physical-level simulator and the inductance extraction tools should be integrated into the existing CAD environment. Hardware Description Language VHDL simulation methods will also require further development. More sophisticated modeling will be required for complex, random logic circuits. Standard delay format could be readily implemented in the usual way, but it is not clear whether this would be effective in superconductive circuits. Also at issue are the effects of signal jitter and of timing-induced probabilistic switching in RSFQ gates. These may combine to make effective hold and setup times in the low BER regime significantly larger than idealized, noiseless circuit simulation would indicate. While the mathematical formalism is well understood, it has not been implemented in CAD for automated checking. Board design and packaging design could proceed using standard 3D EM software (e.g., HFSS) and standard methods, in which models generated in the frequency domain are translated to the time domain for use in physical-level simulations. Software development may be required because the frequency range of interest extends up to 1 THz, and EM modeling must be able to handle superconductors. This will require modification and extension of the commercial software package. 69
Roadmap Table 3.3-1 illustrates the roadmap and milestones for acquisition and development of CAD tools to meet the requirements of the processor and circuits roadmap. The roadmap indicates that most CAD tasks must be completed early in the program to make them available to circuit designers. 70 TABLE 3.3-1. ROADMAP AND MILESTONES FOR ACQUISITION AND DEVELOPMENT OF CAD TOOLS DRC, LVS, PCells Place-and-route Device Models Induction Extraction VHDL Task 2005 2006 2007 2008 2009 2010 Milestone Auto Logic Synthesis Supercon. EM software CAD tool integration CAD training & support Layout & verification Macro circuit designed Simulation & test agree LVS with values Timing design method Macro circuit designed Verify in experiment Unified CAD suite Designs work first pass
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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