Superconducting Technology Assessment - nitrd

CNET
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DRAM-PIM
16 TB
Since the demise of the HTMT project, processor-in-memory technology has advanced as a result of the HPCS
program; the other technologies—RSFQ processors and memory, optical Data Vortex, and holographic storage—
have languished due to limited funding.
Latency, Bandwidth, Parallelism
Attaining high performance in large parallel systems is a challenge. Communications must be balanced with computation;
with insufficient bandwidth, nodes are often stalled while waiting for input. Excess bandwidth would be
wasted, but this is rarely a practical problem: as the number of “hops” between nodes increases, so does the bandwidth
consumed by each message. The result is that aggregate system bandwidth should increase not linearly with
numbers of nodes but as N logN (Clos, hypercube) or N 2 (toroidal mesh) to sustain the same level of random
node-to-node messages per node. Large systems tend to suffer from insufficient bandwidth from the typical
application perspective.
Physical size is another limitation. Burton Smith likes to cite Little’s Law:
latency x bandwidth = concurrency
HSP HSP HSP HSP
CRAM
SRAM
P M
HTMT BLOCK DIAGRAM
Compute Intensive — Flow Control Driven
CRAM
SRAM
CRAM
SRAM
in communications systems which transport messages from input to output without either creating or destroying
them. High bandwidth contributes to high throughput: thus, high latencies are tolerated only if large numbers of
messages can be generated and processed concurrently. In practice, there are limits to the degree of concurrency
supportable by a given application at any one time. Low latency is desirable, but latency is limited by speed-of-light
considerations, so the larger the system, the higher the latency between randomly selected nodes. As a result,
applications must be capable of high degrees of parallelism to take advantage of physically large systems.
CRAM
SRAM
P M P M P M
Data Vortex Network
P M P M P M P M P M
Smart Main Memory
Data Intensive — Data Flow Driven
Latencies
Inter-HSP
400-1000 cycles
Intra-execution
pipeline
10 - 100 cycles
to CRAM
40 - 400 cycles
to SRAM
400 - 1000 cycles
to DRAM
10,000 - 40,000
cycles
DRAM to HRAM
1x10 6 -4x10 6 cycles
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