Superconducting Technology Assessment - nitrd

TABLE 4-4. READINESS OF RSFQ CHIP FABRICATION TECHNOLOGY FOR PETAFLOPS
Element Readiness Requirement
Issues/Concerns
Circuit Speed
Chip Density
Yield
Known-good-die
production
High
High
Moderate
Moderate
2X-5X Increase in J c
1995-98 CMOS
process technology
Greater than 20-30% for
required number of chips
Cryogenic testing
for delivery
4.4 IC CHIP MANUFACTURING CAPABILITY – PROJECTIONS
Degradation of yield due to
higher parametric spreads
Higher device
parametric spreads
Existing yields
not quantified
Cost and time
for full testing
The recent evolution of superconductive IC chip fabrication technology and its extension to 2009 and beyond is
outlined in Table 4-5. The first three columns represent the NGST foundry process through early 2004. The next
column represents a 0.8 µm, 20 kA/cm 2 process that was demonstrated by, and being adopted at, NGST when its
foundry closed in 2004. The final two columns represent the processes anticipated for the proposed program, with
petaflops-scale computing achievable with the technologies introduced in the years 2007 and 2009.
Minimum Feature size (µm)
Junction size (µm)
Junction current density (kA/cm 2 )
Wafer diameter (mm)
Superconducting Wiring Layers
Planarization
Year
Clean Room class
Wafer starts per year
TABLE 4-5. SUPERCONDUCTIVE IC CHIP TECHNOLOGY ROADMAP
1998 2000 2002 2004 2007 2009
1.5
2.50
2
100
4
no
100
12
1.0
1.75
4
100
4
no
100
200
1.0
1.25
8
100
4
no
10-100
200
0.60
0.80
20
100
4
partial
10-100
300
0.60
0.80
20
200
5
partial
10-100
1K
0.25
0.50
50
200
7
yes
1-10
10K
83