Superconducting Technology Assessment - nitrd

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Digital superconducting electronics RSFQ technology has the potential, as identified in the 2003 and 2004 SIA roadmaps, to be a “successor” technology to CMOS for high-performance applications. The 2004 Update to this roadmap stated the problem as: “One difficult challenge related to logic in both near- and the longer-term is to extend CMOS technology to and beyond the 45 nm node sustaining the historic annual increase of intrinsic speed of high-performance MPUs at 17%. This may require an unprecedented simultaneous introduction of two or more innovations to the device structure and/or gate materials. Another longer-term challenge for logic is invention and reduction to practice of a new manufacturable information and signal processing technology addressing ’beyond CMOS‘ applications. Solutions to the first may be critically important to extension of CMOS beyond the 45 nm node, and solutions to the latter could open opportunities for microelectronics beyond the end of CMOS scaling.” EMERGING TECHNOLOGY SEQUENCE RSFQ Phase change Transport enhanced FETs 1-D structures Floating body DRAM UTB single gate FET Resonant funneling Cellular array Nano FG 1.3 WHAT IS RSFQ CIRCUITRY? Rapid Single Flux Quantum (RSFQ) is the latest generation of superconductor circuits based on Josephson junction devices. It uses generation, storage, and transmission of identical single-magnetic-flux-quantum pulses at rates approaching 1,000 GHz. Small asynchronous circuits have already been demonstrated at 770 GHz, and clocked RSFQ circuits are expected to exceed 100 GHz. 1.3.1 JOSEPHSON JUNCTIONS Defect tolerant Biologically inspired SET Molecular QCA Source/Drain engineared FET SET Insulator resistance change UTB multiple gate FET Quantum computing Spin transistor Molecular The Josephson junction (JJ) is the basic switching device in superconductor electronics. Josephson junctions operate in two different modes: switching from zero-voltage to the voltage-state and generating single-flux quanta. The early work, exemplified by the IBM and the Japanese Josephson computer projects of the 1970’s and 1980’s, exclusively used logic circuits where the junctions switch between superconducting and voltage states and require AC power. RSFQ junctions generate single-flux-quantum pulses and revert to their initial superconducting condition. RSFQ circuits are DC powered. Quasi ballistic FET � Risk � Emerging <strong>Technology</strong> Vectors Architecture Logic Memory Non-classical CMOS Figure 1-1. 2004 ITRS update shows RSFQ as the lowest risk (highest maturity) potential emerging technology for processing beyond silicon. 09
1.3.2 RSFQ ATTRIBUTES Important attributes of RSFQ digital circuits include: 10 ■ Fast, low-power switching devices that generate identical single-flux-quantum data pulses. ■ Loss-less superconducting wiring for power distribution. ■ Latches that store a magnetic-flux quantum. ■ Low loss, low dispersion integrated superconducting transmission lines that support “ballistic” data and clock transfer at the clock rate. ■ Cryogenic operating temperatures that reduce thermal noise and enable low power operation. ■ RSFQ circuit fabrication that can leverage processing technology and computer-aided design (CAD) tools developed for the semiconductor industry. Additional discussion of RSFQ technology basics can be found in Appendix D. 1.4 SUMMARY OF PANEL’S EFFORTS The ITRS has identified RSFQ logic as the lowest risk of the emerging logic technologies to supplement CMOS for high-end computing. The panel’s report: ■ Provides a detailed assessment of the status of RSFQ circuit and key supporting technologies. ■ Presents a roadmap for maturing RSFQ and critical supporting technologies by 2010. ■ Estimates the investment required to achieve the level of maturity required to initiate development of a high-end computer in 2010. TABLE 1-1. THE PANEL’S CONCLUSIONS: – Although significant risk items remain to be addressed, RSFQ technology is an excellent candidate for the high-speed processing components of petaflops-scale computers. – Government investment is necessary because private industry has no compelling financial reason to develop this technology for mainstream commercial applications. – With aggressive federal investment (estimated between $372 and $437 million over five years), by 2010 RSFQ technology can be brought to the point where the design and construction of an operational petaflops-scale system can begin.
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: Structurally, a high-end computer w
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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