Superconducting Technology Assessment - nitrd

2.2.3 CORE1 BIT-SERIAL MICROPROCESSOR PROTOTYPES (2002-2005)
Several bit-serial microprocessor prototypes with a very simple architecture called CORE1α have been designed,
fabricated, and successfully tested at high speed in the Japanese Superconductor Network Device project.
Participants in this project include Nagoya, Yokohama, and Hokkaido Universities, the National Institute of
Information and Communications Technology at Kobe, and the International Superconductivity Technology
Center (ISTEC) Superconductor Research Lab (SRL) at Tsukuba in Japan. The project is supported by the New
Energy and Industrial Technology Development Organization (NEDO) through ISTEC.
Bit-serial CORE1α Microprocessor Prototype
A CORE1α microprocessor has two 8-bit data registers and a bit-serial ALU. A few byte shift register memory is
used instead of a RAM for instructions and data. The instruction set consists of seven 8-bit instructions.
These microprocessors have extremely simplified, non-pipelined processing and control logic, and use slow (1 GHz)
system and fast (16-21 GHz) local clocks. The slow 1 GHz system clock is used to advance an instruction from one
execution phase to another. The fast local clock is used for bit-serial data transfer and bit-serial data processing
within each instruction execution phase. A CORE1α10 chip has ~ 7,220 JJs on a 3.4 x 3.2 mm 2 die, and a power
consumption of 2.3 mW.
Bit-serial CORE1ß Microprocessor Prototype
The next design planned for 2005-2006 will be an “advanced bit-serial” CORE1β microprocessor (14 instructions,
four 8-bit registers, and two cascaded bit-serial ALUs) with a 1-GHz system clock, and a 21-GHz local clock. The
CORE1β2 microprocessor is expected to have 9,498 JJs, 3.1 x 4.2 mm 2 size, and power consumption of 3.0 mW.
2.2.4 PROPOSAL FOR AN RSFQ PETAFLOPS COMPUTER IN JAPAN (EST. 2005-2015)
New Focus on Supercomputing
The Japanese are currently preparing a proposal for the development of an RSFQ petaflops computer. This project
is considered to be the next step in the SFQ technology development after the Superconductor Network Device
project in 2007. Organizations to be involved in the new project will include the current participants and new
members to reflect a new focus on supercomputing. The project is expected to be funded through the Ministry of
Education. Table 2-3 shows key target technical parameters of the proposed petaflops system.
New Process
An important element of the new proposal is the development of a new 0.25-µm, 160 kA/cm 2 process with nine
planarized Nb metal layers by 2010, which would allow fabricating chips with 10-50M JJs/cm 2 density, and reaching
a single-chip processor clock frequency of 100 GHz.
Details
The architecture of the proposed RSFQ petaflops computer is a parallel-vector processor with 2,048 processing nodes
interconnected by a network switch to a 200-TB dynamic RAM (DRAM) subsystem at 77 K through 25-GHz
input/output (I/O) interfaces. Each node has eight 100-GHz vector CPUs, with each CPU implemented on one chip
and having 100 GFLOPS peak performance. Each vector CPU has a 256KB on-chip cache and a 32MB off-chip
hybrid SFQ-CMOS memory, the latter being accessible to other processors via an intra-node SFQ switch. As proposed
in 2004, the total system would have 16,384 processors with a peak performance of 1.6 petaflops.
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