Superconducting Technology Assessment - nitrd

Potential for Scaling and Associated Challenges
Figure 3 compares the estimated cell size for standard (1T-1MTJ) MRAM, SMT MRAM using a single minimum-sized
read/program transistor per cell, and NOR Flash. SMT devices have been demonstrated, but integrated SMT MRAM
circuits have not, so that curve assumes technical progress that enables this dense architecture. The solid lines for
the other two technologies indicate the goals and the dashed lines indicate how the cell size might scale if current
known challenges are not completely overcome.
0.1
0.01
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Standard
MRAM
SMT MRAM
FLASH
NOR
30 40 50 60 70 80 90
Figure 3. Estimated cell sizes for the two MRAM technologies compared to NOR Flash for IC technology nodes from 90nm to 32nm. Dashed lines
indicate possible limitations to scaling if some materials and magnetic process challenges remain unresolved.
Scaling MRAM to these future technology generations requires continued improvement in controlling the micromagnetics
of these small bits and the MTJ material quality. The challenges are more difficult for SMT MRAM due
to the smaller bit size required to take advantage of the smaller cell, and the need for increased SMT efficiency to
enable switching at lower current densities. These differences will put more stringent requirements on the in
trinsic reliability and on the quality of the tunnel barrier for SMT devices. Since the SMT technology is less mature
than standard MRAM, it also will be necessary to consider multiple device concepts, material stacks, and corresponding
SMT-MRAM architectures, so that optimal solutions can be identified.
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