Superconducting Technology Assessment - nitrd

ARCHITECTURAL CONSIDERATIONS FOR
SUPERCONDUCTOR RSFQ MICROPROCESSORS
2.1 SUPERCONDUCTOR MICROPROCESSORS –
OPPORTUNITIES, CHALLENGES, AND PROJECTIONS
Although this report focuses on the state of readiness of Rapid Single Flux Quantum (RSFQ) circuit technology,
this chapter will first address the requirements that this technology must satisfy to fill the government’s needs for
high-end computing (HEC).
Any change in circuit technology always calls for a reexamination of the processor architectures that work well with
it. For RSFQ, these adjustments are necessitated by the combination of its high-speed and speed-of-light limitations
on signal propagation between logic elements.
Superconductor processors based on RSFQ logic can potentially reach and exceed operating frequencies of 100
GHz, while keeping power consumption within acceptable limits. These features provide an opportunity to build
very compact, multi-petaflops systems with 100 GHz 64/128-bit single-chip microprocessors to address the
Agency’s critical mission needs for HEC.
In order to be able to initiate the design of a superconductor petaflops-scale system in 2010, the following critical
superconductor architectural and design challenges need to be addressed:
■ Processor microarchitecture.
■ Memory.
■ Interconnect.
The panel believes it will be possible to find and demonstrate viable solutions for these challenges during the
2005-2010 time frame.
The key characteristics of superconductor processors, such as ultra-high clock frequency and very low power
consumption, are due to the following properties:
■ Extremely fast (a few-picosecond) switching times of superconductor devices.
■ Very low dynamic power consumption.
■ Ultra-high-speed, non-dissipative superconducting interconnect capable
of transmitting signals at full processor speed.
■ Negligible attenuation and no skin effect in on- and off-chip niobium transmission lines.
While no radical execution paradigm shift is required for superconductor processors, several architectural and
design challenges need to be addressed in order to exploit these new processing opportunities.
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