Superconducting Technology Assessment - nitrd

The key challenges at the processor design level are:
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■ Microarchitecture
– a partitioned organization.
– long pipelines.
– small area reachable in a single cycle.
– mechanisms for memory latency avoidance and tolerance.
– clocking, communication, and synchronization for 50-100 GHz processors and chipsets.
■ Memory
– High-speed, low-latency, high-bandwidth, hybrid-technology memory hierarchy.
■ Interconnect
– Low-latency on-chip point-to-point interconnect (no shared buses are allowed).
– Low-latency and high-bandwidth for processor-memory switches and system interconnect.
Most of the architectural and design challenges are not peculiar to superconductor circuitry but, rather, stem from
the processor circuit speed itself. At the same time, some of the unique characteristics of the RSFQ logic will
certainly influence the microarchitecture for superconductor processors.
Pipelines
With their extremely high processing rates, fine-grained superconductor processor pipelines are longer than those in
current complementary metal oxide semiconductors (CMOS) processors. The on-chip gate-to-gate communication
delays in 50 GHz microprocessors will limit the space reachable in one cycle to ~1-2 mm. A time to read data from
local, off-chip memory can be up to 50 cycles, while long-distance memory access and interprocessor synchronization
latencies can be easily an order of thousands of processor cycles.
Latency Problem
The sheer size of the latency problem at each design level requires very aggressive latency avoidance and tolerance
mechanisms. Superconductor processors need a microarchitecture in which most processing occurs in close proximity
to data. Latency tolerance must be used to mitigate costs of unavoidable, multi-cycle memory access or other
on-/off-chip communication latencies. Some latency tolerance techniques (e.g., multithreading and vector processing)
that are successfully used in current processors can also work for superconductor processors. Other potential
aggressive architectural options may focus on computation (threads) migrating towards data in order to decrease
memory access latency.
Bandwidth Issues
Petaflops-level computing requires very-high-bandwidth memory systems and processor-memory interconnect
switches. In order to reach the required capacity, latency, and bandwidth characteristics, the memory subsystems
for superconductor processors will likely be built with both superconductor and other technologies (e.g., hybrid
SFQ-CMOS memory). Multi-technology superconductor petaflops systems will need high-speed, high-bandwidth
(electrical and optical) interfaces between sections operating at different temperatures.
Successful resolution of these design issues and the continuing development of the superconductor technology will
allow us to produce a full-fledged 100 GHz 64/128-bit, million-gate microprocessor for HEC on a single chip.