Superconducting Technology Assessment - nitrd

2.6 MICROPROCESSORS – ROADMAP AND MILESTONES
The roadmap below (Figure 2-2) shows the specification and the proposed schedule of the project stages related
to the aggressive development of the architecture and design of the 50 GHz RSFQ processor with local memory
during the 2005-2010 time frame. The roadmap assumes full government funding.
III. Evaluate performance of a 50 GHz 32-bit multi-chip processor with local memory
I. Find architectural
solutions for 50-100 GHz
superconductor processors
1.
Viable
latency-
tolerant
architectural
concept
II. Design a 50 GHz 32-bit multi-chip processor with
local memory
2.
First
instruction
set, micro-
architecture,
chip specs of a
50 GHz 32-bit
processor
MILESTONES
Figure 2-2. 50-GHz multi-chip processor microprocessor design roadmap.
3.
Final
micro-
architecture
and full
processor &
memory
chip specs
The key milestones for the processor microarchitecture development are:
■ 2008: Microarchitecture of a multi-chip RSFQ processor, with its design simulated
and verified for operation at 50 GHz clock frequency.
■ 2010: Integrated functional processor and memory demonstration.
4.
Complete
design of all
processor
and
memory
chips
5.
Integrated
processor
and
memory
demonstrat-
ion
Dec. 2006 Oct. 2007 Mar. 2008 Dec. 2009 Sept. 2010
2005 2006 2007 2008 2009 2010
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