Superconducting Technology Assessment - nitrd

Fig. 12. Trend chart of leakage conductance for comb-to-meander structure showing that oxide fill
eliminates shorts between adjacent comb-to-meander wires over ground etch meander in PCM test
structure. Wire pitch aPXT "m. Ground etch pitch aRXH "m.
Fig. 13. SEM picture of first and second wiring layers crossing
ground moat filled with oxide.
Table 7
Resistor Parameters and Spreads
A. Process Stability
SPC techniques have been applied for in-process monitoring
and for tracking important device performance on
completed wafers. The purpose of in-process tracking is to
catch errors as early as possible, to provide a source of information
to identify where improvements are needed, and for
troubleshooting when problems arise. In-process monitoring
of resistor sheet resistance, film thickness, and feature linesize
for critical layers has been routinely performed.
To track parametric performance, many groups use standard
parametric control monitor (PCM) test chips, which are
fabricated and tested on every wafer [20], [89]–[91]. Computer-aided
testing provides the quantity of data required to
establish a reliable process database and provides rapid and
accurate feedback to the fabrication line. At NGST, more
than 100 device parameters were measured including junction
gap voltage, junction critical currents, junction leakage
current, contact and wire critical currents, capacitor breakdown,
niobium/resistor contact resistance, and inductance
per square. Each parameter was tracked in a separate trend
chart, such as is shown in Fig. 3 for . These data were used
to establish the design rules, which provided the circuit designers
the range of parameters to be expected on any given
chip. This is one important criterion for a integrated circuit
foundry process [28], [66], [90].
Extensive data on the parameter spreads for important circuit
elements such as junctions, resistors, and inductors, indicate
that parameter variations for the present-day processes
are 2–4% 1 for local variations (on-chip), 5% 1
for global variation (across-wafer), and 10% 1 for
run-to-run reproducibility [67]. Local spreads are the most
important in determining circuit size; global variation will
limit yield (i.e., number of good chips), as will run-to-run
targeting. Present-day spreads are consistent with gate densities
of 100 k gates/cm , excluding other yield-limiting
effects such as defect density [16].
DOE or experimental design has become an accepted
framework for process development, optimization, and
reduction of process variance in many manufacturing areas
[92], [93]. It is an efficient tool for determining which factors
affect the outcome of a process. From a cost and time point
of view, it can be beneficial to vary more than one factor
at a time to determine how factors affect the process. DOE
has been used at NGST and by others in the superconductor
electronics community for over a decade in process development
activities [20], [41], [94]. These studies have enabled
rapid progress in developing stable, robust processes.
ABELSON AND KERBER: SUPERCONDUCTOR INTEGRATED CIRCUIT FABRICATION TECHNOLOGY 1527