Superconducting Technology Assessment - nitrd

6.6. SYSTEM INTEGRITY AND TESTING
Because a petaflops-scale superconducting supercomputer is a very complex system, offering major challenges
from a system integrity viewpoint, a hierarchical and modular testing approach is needed. The use of hybrid
technologies—including superconducting components, optical components and conventional electronic components,
and system interfaces with different physical, electrical and mechanical properties—further complicates the system
testing. This area requires substantial development and funding to insure a fully functional petaflops-scale system.
6.6.1 SYSTEM INTEGRITY AND TESTING – STATUS
System-level testing for conventional supercomputers is proprietary to a few companies such as Cray, IBM, Sun,
and NEC. Testing of superconducting supercomputers has not yet been addressed. A limited amount of laboratorylevel
testing of components and sub-modules has been conducted at companies such as NGST, HYPRES, and NEC.
Testing mostly addressed modular approaches at cold temperatures by providing standard physical interfaces and
limited functional testing at high frequencies.
6.6.2 SYSTEM INTEGRITY AND TESTING – READINESS
The readiness for system-level testing is not well understood and requires further development and funding.
6.6.3 SYSTEM INTEGRITY AND TESTING – ISSUES AND CONCERNS
As stated above, testing of a large-scale superconducting system poses major challenges from engineering viewpoint.
Key issues are:
■ Cold temperature and high temperature testing, probes and probe stations: A manufacturable and
automated high-speed testing of SCE circuits operating at 50 GHz clock frequencies requires considerable
development in terms of test fixtures and approaches. Issues such as test coverage versus parametric
testing, use of high frequency, and high frequency at cold temperatures for production quantities needs to
be further developed. The engineering efforts needed are considerable.
■ Assembly testing: Testing becomes further complicated when SCE circuits are grouped at MCM and/or in
3-D modules. Test engineering know-how at this level is minimal. Approaches such as built-in self test can
be utilized but require considerable development effort including fixturing and support equipment issues
along with simple but critical questions such as “what to test” to insure module level reliability. Testing
becomes more challenging when these types of assemblies include other interfaces such as optical I/Os.
■ Production testing: Repeated testing of chips and assemblies require automated test equipment. Such equipment
does not exist even for conventional high-speed electronic systems.
131