Superconducting Technology Assessment - nitrd

Significant activity in the area of digital superconductive electronics has long existed in the United States, Europe,
and Japan. Over the past 15 years, Nb-based integrated circuit fabrication has achieved a high level of complexity
and maturity, driven largely by the promise of ultra-high-speed and ultra-low-power digital logic circuits. An
advanced process has one (JJ) layer, four superconducting metal layers, three or four dielectric layers, one or more
resistor layers, and a minimum feature size of ~1 µm. Today’s best superconductive integrated circuit processes are
capable of producing digital logic IC chips with 10 5 JJs/cm 2 . Recent advances in process technology have come from
both industrial foundries and university research efforts, resulting in reduced critical current spreads and increased
circuit speed, circuit density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for
a static divider (toggle flip-flop) have been demonstrated. Large digital IC chips, with JJ counts exceeding 60,000,
have been fabricated with advanced foundry processes. IC chip yield is limited by defect density rather than by
parameter spreads. At present, integration levels are limited by wiring and interconnect density rather than by junction
density, making the addition of more wiring layers key to the future development of this technology.
Recent advances in process technology have come from both
industrial foundries and university research efforts.
Nb-based superconductive IC chip fabrication has advanced at the rate of about one generation, with a doubling
of J c , every two years since 1998. Increasing J c enables increasing digital circuit speed. This is illustrated in Figure
4-3, a plot of static divider speed from several of sources versus J c. Points beyond 8 kA/cm 2 represent single
experimental fabrication runs, not optimized processes. Theoretically, divider speed should approach 1,000 GHz
(1 THz), however, the process and layout must be optimized to reduce self-heating effects in junctions with J c beyond
100 kA/cm 2 . The first generation Nb process discussed in Section 4.6 should be based on 20 kA/cm 2 , 0.8 µm
diameter junctions with six superconducting metal layers. Static dividers fabricated in this process have achieved
speeds of 450 GHz, which should enable complex RSFQ circuits with on-chip clock rates of 50 to 100 GHz.
Figure 4-3. Demonstrations of RSFQ circuit speed with increasing J c
80
f max (GHz)
1000
900
800
700
600
500
400
300
200
1 10
J (kA/cm c
100
2 100
)