Superconducting Technology Assessment - nitrd

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INTRODUCTION The request for this assessment was motivated by the government’s assessment that conventional technology for high-end computing (HEC) systems is finding it more and more difficult to achieve further increases in computational performance. A panel of experts in superconductive electronics, high-performance computer architectures, and related technologies was formed to conduct this study. The composition of the panel is presented in Appendix B. In summary, the charge to the panel was to: “...conduct an assessment of superconducting technology as a significant follow-on to silicon for component use in high performance computing systems available after 2010. The assessment will examine current projections of material science, device technology, circuit design, manufacturability, and general commercial availability of superconducting technology over the balance of the decade, identify programs in place or needed to advance commercialization of superconducting technology if warranted by technology projections, and identify strategic partnerships essential to the foregoing. First order estimates of the cost and complexity of government intervention in technology evolution will be needed. The assessment will not directly investigate potential high-end computer architectures or related non-superconducting technologies required by high-end computers other than those elements essential to the superconducting technology projections.” The full text of the formal charge to the panel is given in Appendix A. 1.1 NSA DEPENDENT ON HIGH-END COMPUTING The NSA mission is dependent on HEC for cryptanalysis, natural language processing, feature recognition from image analysis, and other intelligence processing applications. NSA applications touch the extremes of supercomputing resource use: numerically intensive computation, high-volume data storage, and high bandwidth access to external data. As the use of electronic communications increases, so too does the volume of data to be processed and the sophistication of encryption mechanisms; thus, the need for HEC escalates. NSA’s mission is dependent on high-end computing; its applications touch the extremes of supercomputing resource use: – Numerically intensive computation. – High-volume data storage. – High-bandwidth access to external data. For the past two decades, HEC systems have evolved by leveraging a large commodity microprocessor and consumer electronics base. However, there is now increased concern about the divergence of this base and the government’s HEC technology needs. There are many other potential government and private sector applications of HEC. Some of these are discussed in Appendix E: Some Applications for RSFQ. (The full text of this appendix can be found on the CD accompanying this report.) 07
1.2 LIMITATIONS OF CONVENTIONAL TECHNOLOGY FOR HIGH-END COMPUTING In 1999, the President’s Information Technology Advisory Committee (PITAC) wrote the following in its Report to the President-Information Technology Research: Investing in Our Future (Feb 1999): “…Ultimately, silicon chip technology will run up against the laws of physics. We do not know exactly when this will happen, but as devices approach the size of molecules, scientists will encounter a very different set of problems fabricating faster computing components.” 1.2.1 CONVENTIONAL SILICON TECHNOLOGY NOT THE ANSWER NSA experts in HEC have concluded that semiconductor technology will not deliver the performance increases that the government’s computing applications demand. Complementary metal oxide semiconductors (CMOS) is becoming less a performance technology—vendors such as Intel are voicing reluctance to seek 10 GHz clock speeds—and more a capability technology, with transistor counts of several hundred million per chip. The high transistor counts make it possible to put many functional units on a single processor chip, but then the on-chip functional units must execute efficiently in parallel. The problem becomes one of extracting parallelism from applications so that the functional units are used effectively. Unfortunately, there are applications for which on-chip parallelism is not the solution; for such applications, blazing speed from a much smaller number of processors is required. For supercomputers, continuing reliance solely on a CMOS technology base means a continuation of the trend to massively parallel systems with thousands of processors. The result will be limitations in efficiency and programmability. In addition, at today’s scale, the electrical power and cooling requirements are facing practical limits, even if ways were found to efficiently exploit the parallelism. For example, the Japanese Earth Simulator system, which has been ranked number one on the list of the top 500 installed HEC, consumes over 6 megawatts of electrical power. 1.2.2 SUPERCOMPUTING RSFQ A VIABLE ALTERNATIVE The Silicon Industry Association (SIA) International Technology Roadmap for Semiconductors (ITRS) 2004 update on Emerging Research Devices has many candidate technologies presently in the research laboratories for extending performance beyond today’s semiconductor technology. Superconducting Rapid Single Flux Quantum (RSFQ) is included in this list and is assessed to be at the most advanced state of any of the alternative technologies. RSFQ technology has the potential to achieve circuit speeds well above 100 GHz with lower power requirements than complementary metal oxide semiconductor (CMOS), making it attractive for very-high-performance computing, as shown in Figure 1-1. 08 Superconducting RSFQ is assessed to be at the most advanced state of any of the alternative technologies.
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19: 01 This document presents the resul
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: Structurally, a high-end computer w
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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