Superconducting Technology Assessment - nitrd

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SUPERCONDUCTIVE CHIP MANUFACTURE The promise of digital Rapid Single Flux Quantum (RSFQ) circuits is now well established by the results that have come out of various research laboratories. Basic digital device speeds in excess of 750 GHz have been demonstrated. Today, superconductive electronic (SCE) chip manufacturing capability is limited to 10 4 –10 5 Josephson junctions (JJs) (equivalent to a few thousand gates) with clocked logic speeds of less than 20 GHz, due to fabrication in an R&D mode with old fabrication equipment and technologies. The use of SCE to achieve petaflops-scale computing will require fabrication of large-area, high-density, superconductive IC chips with reasonable yield. In this section, the panel will: ■ Assess the status of IC chip manufacturing for superconductive RSFQ electronics at the end of calendar year 2004. ■ Project the capability that could be achieved in the 2010 time-frame. ■ Estimate the investment required for the development of RSFQ high-end computers within approximately five years. The use of SCE to achieve petaflops-scale computing will require fabrication of large-area, high-density, superconductive IC chips with reasonable yield. 75
Table 4-1 summarizes the roadmap for chip production for aggressive government, moderate, and no funding scenarios. Potential exists for further improvement of the technology beyond 2010. That vision is summarized in Table 4-2. The roadmap established by the panel, detailed in section 4.6, provides for the development of two new generations of RSFQ chip technology by 2010 to be developed in a pilot line and then transferred to a manufacturing line. The first generation process, which is projected for 2007, builds on the most advanced process demonstrated to date, adding minimal improvements but using newer equipment based on 250 nm complementary metal oxide semiconductors (CMOS) processing. The second generation process, which is projected for 2009, assumes narrower line widths (with the same 250 nm lithographic tools), a modest increase in critical current density, J c, and the introduction of well understood planarization processes from CMOS. Beyond 2010, a significantly denser, faster chip technology could be developed, but in a time frame, and requiring resources, outside of the roadmap outlined in this study. This scenario assumes migration to 90 nm or better equipment and processes, moving to layer counts comparable to future CMOS technology, and aggressively increasing the current density to achieve junction speeds at the limit of Nb technology (1,000 GHz). 76 Aggressive Funding Moderate Funding No Funding TABLE 4-1. SCE INTEGRATED CIRCUIT CHIP MANUFACTURE ROADMAP – Establishment of a modest volume manufacturing capability and infrastructure for delivery of known good die. – Clock rates of 50 GHz or higher, densities of 1-3 million JJs per cm 2 by 2010. Yield and manufacturability established and costs understood. – Establishment of low volume pilot line/R&D capability with some upgrades to present R&D capabilities. – Pilot/R&D capability demonstrations of density and clock rates of interest by 2014. Yield and manufacturability will not be demonstrated. – Continued R&D efforts in academic and foreign laboratories. Low continuity of effort. – Modest increases in clock rate and circuit densities in R&D demonstrations. Performance, gate density, and manufacturability inadequate for petaflops computing. $125 M ~$60 M 0
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87: 04 By 2010 production capability fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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