Superconducting Technology Assessment - nitrd

3.2.1 MEMORY – HYBRID JOSEPHSON-CMOS RAM
SFQ
input
Figure 3.2-1. Hybrid Josephson-CMOS RAM operates at 4 K. The input and output signals are single-flux-quantum pulses.
The hybrid JJ-CMOS RAM uses CMOS arrays at 4 K for data storage, combined with JJ readout to reduce READ
time and eliminate the power of the output drivers. In order to access the CMOS, it is necessary to amplify SFQ
signals to volt levels. Extensive simulations and experiments have been performed at UC Berkeley on this approach
for several years. Furthermore, the core of the memory is fabricated in a CMOS foundry and benefits from a highly
developed fabrication process, and the Josephson parts are rather simple. This combines the advantages of the
high density achievable with CMOS and the speed and low power of Josephson detection. The entire memory is
operated at 4 K, so it can serve as the local cryogenic memory for the processor. A 64-kb CMOS memory array fits
in a 2 mm x 2 mm area. As CMOS technology continues to develop, the advances can be incorporated into this
hybrid memory. The charge retention time for a three-transistor DRAM-type memory cell at 4 K has been shown
to be essentially infinite, so that refreshing is not required. The operation is as though it were an SRAM cell, even
though DRAM-type cells are used. Figure 3.2-1 illustrates the overall architecture.
Hybrid JJ-CMOS RAM Status
The experimental part of this work used standard foundry CMOS tested at 4 K. CMOS circuits from four different
manufacturers. A BSIM (a simulation tool developed at the University of California, Berkeley) model (industry standard
at 300 K) was developed for 4 K operation and gives very good agreement with ring-oscillator measurements,
which show a speed-up of ~25% by cooling from 300 to 4 K. It is inferred that the decoder/driver circuits are similarly
enhanced upon cooling.
Josephson circuits are used only at the input and output. Very fast, extremely low power, low impedance Josephson
detectors are used to sense the bit lines and generate SFQ output pulses. The input requires amplification of the
mV SFQ signals to volt-level input to the CMOS driver/decoder. Several circuits have been evaluated; a hybrid
combination of Josephson and CMOS components is presently used.
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Hybrid JJ-CMOS interfaces
Address buffers
Row decoder 2 8 =256
WL Read
C=256xC
BL Write
C=256xC s/d
Word Decoder
BL Read
WL Write
C=256xC
Read current path
RSFQ detector/driver