Superconducting Technology Assessment - nitrd

3.1.5 RSFQ PROCESSORS – ISSUES AND CONCERNS
Identifying and addressing important issues early will reduce the risk for demonstration of a high-performance
RSFQ processor.
TABLE 3.1-6. ISSUES FOR RSFQ PROCESSOR TECHNOLOGY DEVELOPMENT AND RESOLUTION
Issue
– Margins are impacted by parameter spreads, gate optimization,
current distribution cross-talk, signal distribution cross-talk,
noise, bias and ground plane currents, moats and flux trapping,
and timing jitter.
– Shrinking margins have recently been reported for large circuits
(>103JJ’s) for clock rate above 10 GHz.
– Low gate density.
– Clock skew.
– On-chip velocity ~100µm/ps.
– At 50 GHz, distance within clock cycle is 2 mm.
– Thermal and environmental noise increases errors.
– All I/O lines are subject to noise pickup and cross-talk.
– Timing errors limit clock frequency.
– All junctions contribute jitter.
– Noise enhances jitter.
– Magnetic flux trapped in superconducting films can shift the
operating point of devices.
– Local magnetic field and large transients sources of trapped flux.
– Dense chips require many amperes of current.
– No vendor for superconducting MCM.
Resolution
– Isolate on-chip power bus and data lines from gate
inductors by additional metal layers.
– Control on-chip ground currents by using differential
power supply.
– Optimize design for timing.
– Improve litho to shrink features.
– Increase number of superconducting layers so power,
data transmission lines, and gates are on separate levels.
– Increase gate density to reach more gates in clock cycle.
– Generate clock on-chip.
– Resynchronize local clocks.
– Timing tolerant design and microarchitecture.
– Reduce environmental noise by isolating and filtering.
power and I/O lines.
– Reduce environmental noise.
– Reduce number of JJs in data and clock.
distribution network.
– Improve timing analysis and simulation using VHDL.
– Improved shielding and filtering.
– Develop methodology for design of moats to trap
magnetic flux away from circuits.
– Supply RF bias-current from RT to ~40 K.
– RF-DC power converter at ~ 40 K.
– Use HTS power leads from 40 to 4 K.
– Extensive current reuse on chip and between chips.
– Decision between internal or vendor development.
Appendix G: Issues Affecting RSFQ Circuits provides an expanded discussion of these topics. (The full text of this
appendix can be found on the CD accompanying this report.)
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