Superconducting Technology Assessment - nitrd

Power and bias current
Power is dissipated continuously in the series resistors used to bias each junction. P ~ 0.5I CV DC per junction, where
V DC is the DC voltage power bus. This static power dissipation dominates on-chip power dissipation. Ohmic dissipation
can be reduced by using the smallest I C consistent with the required BER, using designs with the fewest
junctions (e.g., using passive rather than active transmission lines), and reducing the on-chip voltage supply as
much as possible consistent with gate stability and preserving margins.
For a 2 mV bias supply, the static power dissipation is 100 nW/JJ. If one accepts ~10% reduction in gate margin
(e.g., from 30% to 20%), one can reduce V DC to ~ 10 -5 F(GHz). At 50 GHz, V DC = 0.5 mV and the static power
dissipation is ~ 35 nW/JJ. Power is dissipated in every JJ in both the logic and clock networks at the SFQ switching
rate, P = 2 x 10 -15 f SFQI C = 2 x 10 -19 watts/Hz per JJ (~1 electron-volt) or 0.2 nW/GHz/JJ. At 50 GHz, the
irreducible SFQ power is = 10 nW/JJ.
A recent concept (called SCCL, Self-Clocked Complementary Logic) mimics CMOS by replacing bias resistors with
junctions, forming a complementary pair wherein one and only one of the pair switches each clock cycle, and
eliminates the ohmic loss. A few gates have been simulated and limited experiments have been performed
successfully, but it has not been developed for a general gate family. An added value of this approach is incorporation
of the local clock into the gate, eliminating the need for separate clock distribution circuitry. Normally, clock
distribution has a splitter per gate that increases ohmic power, is an added source of jitter that reduces margins in
large circuits, and occupies valuable space on-chip.
Chips with a large number of junctions require large bias currents. Even assuming all JJs are at minimum I C of 100
µA, a 10 6 -JJ chip will require 100 A. Efficient methods of supplying bias current to the chips will have to be
demonstrated for large circuits. A method to bias large circuit blocks in series (referred to as current recycling or
current re-use) will be essential for large junction-count chips in order to reduce the total current supplied to the
chip to a manageable value. Both capacitive and inductive methods of current recycling have been demonstrated
at a small scale. Current recycling becomes easier at higher J C. There have been no demonstrations of current
recycling for large circuit blocks or for a large number of stages, so this will require development. Current recycling
can reduce the heat load in the power lines into the cryostat, but does not reduce the on-chip power dissipation.
For current re-use, the ground planes under adjacent circuit blocks must be separated and subsequent blocks
biased in series. It will also be necessary to isolate SFQ transients between adjacent blocks. This may be achieved
by low pass filters, but will need to avoid power dissipation in the filters. Series inductance could provide high
frequency isolation; the inductors could be damped by shunting with suitable resistance, such that there is no DC
dissipation. Capacitive filtering may be problematic.
Efficient methods of supplying bias current to the chips need to be demonstrated for large circuits. The problem is
to supply a large, low noise, stable current to the chip though the thermal-mechanical interface. Except for
minimizing the number of JJs, power reduction does not reduce the current required to power the chip. This is
discussed below.
Flux trapping
All Josephson circuits are sensitive to local magnetic fields. This sensitivity derives from the small size of the
magnetic flux quantum; one flux quantum is equivalent to 2 x 0 -7 gauss in a 1-cm 2 area. (The magnetic field of the
earth is ~ 0.4 gauss.) JJ circuits are shielded from local magnetic fields, such as the earth’s field, by high
permeability shields. The field inside “good” shields can be as low as a few milligauss. Flux trapping occurs at
unpredictable locations in superconducting films as they are cooled through their superconducting transition
temperature, T C. Flux trapped in ground planes can shift the operating point of SFQ circuits. One method for
alleviating this effect is to intentionally trap the flux in holes (called moats) placed in the ground plane. One tries
to place the moats where the trapped flux will not affect the circuit. There is no standard system for designing
and locating moats. When flux trapping is suspected as the problem for a chip under test, the procedure is to
warm the chip above T C and cool it again, possibly after changing its orientation or position. If the behavior changes
every time, the conclusion is that flux trapping is at fault. The assumption is that flux trapping is not reproducible.
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