Superconducting Technology Assessment - nitrd

Fig. 11. Ground plane planarization process. (a) Deposit first
100 nm of the niobium ground plane, mask, and etch to define
circuit features. (b) Strip photoresist and deposit second 50 nm
of the niobium ground plane. (c) Mask ground contacts and
anodize niobium ground plane to the desired thickness (144 nm).
(d) Completed process showing 52% reduced step height (112 nm)
compared to ground etch step height if unfilled (235 nm).
film (typically 50 nm) is deposited, which completely covers
the ground etch layer as shown in Fig. 11(b). The total niobium
ground plane thickness is 150 nm, and the ground etch
areas are filled with 50 nm of Nb. Next, the ground contact
areas are masked, and the entire niobium ground layer including
the niobium in the ground etch areas is anodized. The
thinner niobium in the ground etch areas, deposited by the
second deposition, is converted completely to Nb O (typically
122 nm thick) before the desired thickness of Nb O on
the ground plane is reached (typically 144 nm). Fig. 11(c) illustrates
the anodization of the ground plane and ground etch
areas. The completed structure after anodization and photoresist
strip is shown Fig. 11(d) and illustrates the reduction
in step height from 235 nm without ground etch oxide
fill to 112 nm with ground etch filled with Nb O .Inthis
case, the degree of planarization is about 52%, and typical
across-wafer step height variation is on the order of only
3%.
Planarization by anodization is a relatively simple process
and requires only a minor change to the standard niobium
ground plane anodization step. As shown in Fig. 12, this
process has dramatically reduced electrical shorts, as measured
by comb-to-meander test structures, between adjacent
wires over ground etch steps. With the exception of a few
random electrical shorts due to defects (particles), electrical
shorts in the first wiring layer were eliminated, and the reduction
in step height has increased wire critical current by
74% to 40 mA/ m. Fig. 13 is a SEM picture of part of a
series-biased circuit showing the high quality of the first and
second wiring layers crossing over an Nb O oxide-filled
moat to connect to a circuit on an isolated ground plane.
E. Resistor Fabrication and Parameter Spreads
As the increases, higher resistivity materials are required
for shunted junctions to minimize circuit parasitics
in RSFQ circuits. Attractive materials are sputter-deposited
thin films of MoN [49] or NbN [69] because their resistivity
can be adjusted over a wide range by varying the
amount of nitrogen. Both materials are easily dry etched
in SF using existing RIE tools and recipes. In the NGST
8-kA/cm process, a MoN film, adjusted to 5.0 /square
[18], is used for shunting junctions and biasing. The
8-kA/cm process also includes a 0.15 /square Mo/Al
bilayer film [18] that is used for extremely low value shunts
or for breaking a superconducting loop. At the present level
of integration, both resistors have acceptable within-wafer
sheet resistance spreads of 2.9% 1 for MoN and 3.2%
1 for Mo/Al. The spreads are almost entirely due the
spatial variation in film thickness and could be reduced
substantially by improving deposition geometry and sputter
gun uniformity. Important resistor parameters and spreads
are summarized in Table 7. Wafer-to-wafer variation of sheet
resistance, as measured by standard Van der Pauw structure,
is less than 6% for both resistors and indicates that these
resistors have good process stability. The next-generation
20-kA/cm process uses NbN resistors [69] targeted to
an optimum 8.0 /square. Preliminary results suggest that
NbN resistor parameter spreads and run-to-run stability are
comparable to MoN .
V. INTEGRATED CIRCUIT MANUFACTURABILITY
In order to produce working integrated circuits of any reasonable
size, a reliable process is needed. In order to establish
reliability, the foundry process capability needs to be understood.
This understanding derives from application of techniques
such as statistical process control (SPC), which can
be used to track long-term behavior in the process. Proven
in many manufacturing industries, including semiconductor
manufacturing, SPC and design of experiments (DOE) improve
efficiency and effectiveness in problem solving and
process maintenance efforts. SPC is a powerful tool that encompasses
a wide range of statistical techniques, including
control charts, Pareto charts, and cause and effect diagrams
[88]. The goal of SPC is to determine the inherent process
variation, identify common-cause versus special-cause variation,
set realistic parameter specifications, and prevent processes
from going out of control while working to reduce the
inherent process variability. The process variability can then
be reduced with techniques such as DOE. We discuss the application
of these tools to superconductor integrated circuit
manufacturing.
1526 PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004