Superconducting Technology Assessment - nitrd

Although cooling of the 4 K circuits by immersion in LHe may be the most straightforward approach cryogenically,
doing so would produce significant technical issues on the system integration front: large diameter plumbing
would be required to carry the helium gas back to be recondensed and utilizing the enthalpy of the gas in order
to pre-cool the I/O lines requires a complicated heat exchanger. Most importantly, the 4 K components would need
to be surrounded by a He leak-tight vessel and then a vacuum space. Either the leads would have to travel to
elevated temperatures with the gas, necessitating long signal travel times, or they would travel a shortest distance
path that would require cryogenic vacuum feed-throughs for each of the leads. It seems likely that this approach
practical only if substantial cold memory exists in the system so that only computational results are shipped to the
room temperature. Otherwise, millions of high speed I/Os are needed
Cooling by conduction using plates made from high thermal conductivity materials such as copper seems a more
viable alternative when SCE chips, MCMs, PCBs, and I/Os are all in the same vacuum space. These plates would
either have direct thermal connections to a cold plate, cooled by the refrigerator, or have liquid helium running
through a set of engineered sealed passages (e.g. micro-channels or pores of Cu foam) within the plates
themselves. Such systems have recently been extensively worked to provide extreme rates of heat removal from
above room temperature for power amplifiers and the same physics will apply. Whether both the liquid and gas
phase of He can be present might need to be investigated. Conduction cooling places greater demands on the
thermal design of the system but the technical issues are familiar. Low thermal conductance paths from the chip
to the cold head are essential. The temperature difference between the component being cooled and the cold box
is a key issue even when large refrigerators are used to cool superconducting electronic devices. Given the severe
energy penalty for compensating for this gradient by lowering the cold-plate temperature, bit-error tests should be
performed for 20 KA/cm 2 circuits as a function of bias temperature as early as possible. For 1KA/cm 2 devices there
is experimental evidence that circuits designed for 4.2 K operation still function well as high as 5.5 K due to the
slow dependence of critical current (I c) on temperate (ref. HYPRES).
Serious consideration should be given toward reducing the refrigeration load through the use of high temperature
superconducting (YBCO or MgB2) cables or optical leads in conjunction with mid temperature (e.g. 30- 40 K)
intercepts. More details are provided in the “Cables” section.
Vibration can be a serious problem for superconducting electronics if the total magnetic field at the circuits is not
uniform and reproducible. Good cryo-packaging practice requires both careful attention to magnetic shielding,
minimization of vibration and relative motion of circuit components. If it proves essential, the sensitive electronic
components can be mounted using a stiff (high resonant frequency) cold mass support system that has a low heat
leak and is cooled via a flexible cooling strap attached to the cold plate. Keeping the strap short length minimizes
the temperature drop and also reduces the vibration isolation achieved. The cryocooler itself can be mounted with
flex mounts on the cryostat vacuum vessel, which has more mass than the cooled device.
The reliability issues can be mitigated by using smaller cryocooler units around a central large scale cryogenic cooling
unit. This approach adds modularity to the system and allows for local repair and maintenance while keeping the
system running. However, the design issues resulting from the management of many cryocoolers working together
are yet not well explored.
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