Superconducting Technology Assessment - nitrd

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Background Superconducting Technology Assessment Letter of Promulgation August 2005 This Superconducting Technology Assessment (STA) has been conducted by the National Security Agency to address the fundamental question of a potential replacement for silicon complementary metal oxide semiconductor (CMOS) in very high-end computing (HEC) environments. Recent industry trends clearly establish that design tradeoffs between power, clock and metrology have brought CMOS to the limits of its scalability. All microprocessor firms have turned to multiple cores and reduced power in efforts to improve performance. Increased parallelism on a chip permits some architectural innovation, but it also increasingly shifts issues of performance gains into software application environments, where there are already many practical limits to scalability of performance. For many demanding applications in the U. S. national security, scientific, medical and industrial sectors, availability of higher-performance components in well-balanced HEC environments is essential. Alternatives to CMOS must therefore be found. The Semiconductor Industry Association (SIA) International Technology Roadmap for Semiconductors (ITRS) has identified Superconducting Rapid Single Flux Quantum (RSFQ) technology as the most promising technology in the continuing demand for faster processors. There has been steady progress in research in this technology, though with somewhat weaker efforts at development and industrialization. This assessment is an in-depth examination of RSFQ technologies with the singular objective of determining if a comprehensive roadmap for technology development is possible, aiming for industrial maturity in the 2010-2012 timeframe. The goal would be an RSFQ technology set sufficient to support development of true petaflop-scale computing at the end of this decade. Methodology A team of national experts in superconducting technologies was empanelled to conduct this assessment. It was chaired by Dr. John Pinkston, former Chief of Research, NSA. Membership is shown in Appendix B and included experts in processor architectures, several types of memories, interconnects, design and manufacturing in these technologies. The panel heard from academic, industrial and government experts in the field and reviewed available superconducting documentation. The panel also had the benefit of presentations and discussions with two leading HEC architects on system-level issues that could conceivably impact the use of RSFQ technologies. The panel had lengthy internal discussions on the mutual dependencies of various superconducting components. Availability, technical issues, development schedules and potential costs were discussed at length. The resulting roadmap represents a consensus of views with no substantial dissension among panel members. The panel was enjoined from examining HEC architectural issues and systems-level options, other than those bearing directly on technology envelopes (e.g., is a 50 Ghz clock a sufficient goal?).
Summary of Findings The STA concluded that there were no significant outstanding research issues for RSFQ technologies. Speed, power and Josephson Junction density projections could be made reliably. Areas of risk have been identified and appropriately dealt with in the roadmap, with cautionary comments on mitigation or alternatives. Memories are clearly one such area, but this report concludes that the field suffers more from lack of research than available alternatives. The assessment, in fact, identifies several memory alternatives, each of which should be pursued until technology limits are clearly understood. Development of RSFQ technologies to sufficient levels of maturity, with appropriate milestones, could be achieved in the time frame of interest but would require a comprehensive and sustained government funded program of approximately $100M/yr. The panel concluded that private sector interests in superconducting RSFQ would not be sufficient to spawn development and industrialization. It is, of course, NSA’s role to turn these STA findings into specific actions in partnership with national security community and other federal HEC users having extreme high end computing needs and the vision to pursue the performance goals that superconducting RSFQ appears to offer. The undersigned government members of this study would like to commend our industry and academia participants for the balanced and constructive assessment results. ______________________________ ______________________________ Dr. Fernand Bedard Dr. Nancy K. Welker ______________________________ ______________________________ George R. Cotter Michael A. Escavage ______________________________ Dr. John T. Pinkston
Page 1: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: Structurally, a high-end computer w
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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