Superconducting Technology Assessment - nitrd

Integrated MRAM and RSFQ Electronics
MRAM circuits are presently fabricated in a back-end process, after standard CMOS electronics processing. This
integration scheme is one of the reasons that MRAM is viewed as a strong candidate for a future universal embedded
memory. MRAM could potentially be fabricated as a front-end process to a superconducting back-end technology
(or vice versa), providing a high-performance, nonvolatile, monolithic memory solution for RSFQ technology. Some
of the issues that must be addressed in pursuing this monolithic option are: effects of low temperatures on MRAM,
compatibility of the required currents, power dissipation, and resistance matching. In addition, one needs to
consider compatibility of MRAM and RSFQ processing with respect to materials and processing temperatures.
MRAM devices have higher MR at low temperature due to a reduction of thermal effects that depolarize the
spin-polarized tunneling electrons. A 50% increase in MR from RT to 4.2 K is typical, e.g., from MR = 40% to MR
> 60%. The higher MR combined with lower noise levels inherent at low-temperature operation would provide a
much larger useable signal, and therefore much faster read operations. Temperature also has a big effect on the
magnetics of the MRAM devices. Because of their small magnetic volume, these devices experience significant
thermal fluctuations at room temperature, which increase the requirements for minimum switching field and
minimum layer thickness to prevent thermally-activated write errors. MRAM bits for cryogenic temperatures can be
designed with thinner layers and lower switching fields, reducing write currents. In large arrays, one always
observes a distribution of switching fields. These distributions require significantly higher write currents than the
mean switching current, typically at least 6σ above the mean for Mbit memories. The two main sources of these
distributions are thermal fluctuations and micromagnetic variations, because bits in arrays are not exactly identical.
At cryogenic temperatures, the thermal contribution will be negligible, leaving only the contribution from
micromagnetic variation. Thus, unless there are unforeseen micromagnetic issues, the magnetic distributions
should be narrower at low temperatures, leading to a further reduction in the write current. Overall, one might
expect a 30% to 50% reduction in write current at cryogenic temperatures for standard MRAM and 10% to 30%
for SMT MRAM.
Figure 4 shows how the minimum write-current for an SMT MRAM element would scale with IC lithography in
a one-transistor-per-cell architecture. This plot assumes some improvement in spin transfer efficiency in order to
complement the resistance of a minimum-sized pass transistor. The SMT cell is designed to maintain an energy
barrier of 90 kT at normal operating temperatures. Thus, a 2-Ω SMT device, 90 nm in size, would require a bias of
0.2 mV to supply the desired switching current of 0.10 mA. The same resistivity material at the 45-nm node would
have a device resistance of 8 Ω; the corresponding switching current of ~0.04 mA would require a bias of only
0.24 mV. Since these are small bias values, it may be safe to conclude that providing the necessary drive
currents for SMT cells from RSFQ circuits is less of an issue than for SMT MRAM-on-CMOS, where larger voltages
are required to overcome ohmic losses. Moreover, as described before, at lower temperatures, the energy barrier
requirement becomes essentially non-existent, so that the free layer can be made much thinner, limited only by the
practical thickness needed for a good quality film. With further reduction in device dimensions below 90 nm, the
thinner free layer would decrease the magnetic volume by ~ another factor of two, leading to a reduction in the
critical current of up to 50% at cryogenic temperatures, compared to the numbers on this plot. Thus, it should be
possible to directly connect superconducting JJ electronics to SMT MRAMs, even without the improvements in
spin-transfer efficiency desired for room-temperature SMT operation.
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