Superconducting Technology Assessment - nitrd

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Ground Plane Counter/B arrier/Base Electrodes Resistor Resistor Wire 3 Plug Passivation Silicon Substrate Wires, Ground Plane, Plugs Oxide Passivation Wire 2 Ground Plane Figure 4-4. Notional cross-section of the superconductive IC chip fabrication process illustrating salient features of an advanced process, which includes four interconnect levels, planarization, and plugs. The leap to gate densities and feature sizes needed for petaflops cannot be achieved in a single step. Sequential improvements will be needed, commensurate with the funding available for the process tools and facilities. Semiconductor technology has scaled by a factor of 0.7x in feature size and 2.5x in gate density for each generation, each of which has taken about three years and a substantial capital investment. However, much of the delay in advancing semiconductor IC chip technology was due to the lack of advanced process tools, especially in the area of photolithography. The panel expects to achieve 0.8 µm junction sizes in the next generation, because the tools and methodologies are already available. In fact, NGST, in collaboration with JPL, demonstrated a 0.8 µm junctionbased circuit fabrication process and was on the way to adopting it as standard when its Nb foundry closed in 2004. Further reduction in feature size and other process improvements will occur in subsequent generations. 4.5.2 IC CHIP MANUFACTURE – DEVICE AND CIRCUIT SPEED Wire 1 RSFQ gate speed is ultimately limited by the temporal width of the quantized pulses. For junctions with critical current I c and resistance R, this width is proportional to Φ 0/I cR, where Φ 0=2.07mV-ps is the superconducting flux quantum. The maximum operating frequency of the simplest RSFQ gate, a static divider , is f 0 =I cR/Φ 0. Maximum speed requires near-critical junction damping, with 2πf 0RC ~ 1, where C is the junction capacitance. Then f 0 = (J c/2πΦ 0C’) 1/2 , where J c and C’ are the critical current density and specific capacitance, respectively. These parameters depend only on the thickness of the tunnel barrier. Because C’ varies only weakly with barrier thickness, while J c varies exponentially, f 0 is approximately proportional to J c 1/2 . Plug 85
Table 4-6 shows how gate speed depends on critical current density and JJ size. The last three columns list ranges of operating frequency. For a typical Nb RSFQ fabrication process available today, J c = 2 kA/cm 2 , and f 0 ~ 170 GHz. However, for both superconductive and semiconductor digital technologies, the maximum clock speed of VLSI circuits is well below f 0,the speed of an isolated gate. The input and output signals for a logic gate are generally aperiodic, so the SFQ pulses must be well-separated. Since RSFQ gates are generally clocked, timing margins must be built in to ensure minimum clock-to-data and data-to-clock separation. Several timing methods in large, complex circuits—including concurrent or counterflow clocking, dual rail, and event-driven logic—are under investigation. The last two columns list clock speed ranges for asynchronous circuits (such as shift registers) and complex, clocked circuits (ranging from adders and multipliers to processor IC chips, respectively). For example, experience, both experimental and theoretical, shows that complex circuits in 2 kA/cm 2 technology can be clocked at 20 – 40 GHz. Scaling J c up to 20 kA/cm 2 results in f 0 ~ 450 GHz, and the panel anticipates that complex circuits built with this technology will be able to operate at speeds ranging from 50 to over 100 GHz. Figure 4-5 is a graphical illustration of these projections. 4.5.3 IC CHIP MANUFACTURE – CIRCUIT DENSITY AND CLOCK SPEED Successive superconductive IC chip fabrication process generations will result in improved RSFQ circuit performance, with clock rates of at least 100 GHz possible. Because signals propagate on superconductive microstrip lines at one-third the speed of light in vacuum, interconnect latency is comparable to gate delay in the 100 GHz regime. Signal propagation distances must be minimized by increasing gate density, using both narrower line pitch and additional superconductive wiring levels. This may be even more important to increasing the maximum clock rate than smaller junctions and higher critical current density. Thus, successive IC generations focus on improved gate density (by reducing line pitch and increased number of interconnect layers) as well as gate delay (by reducing junction size). These process improvements are listed and evaluated in Table 4-7. 86 J c TABLE 4-6. DEVICE PARAMETERS AND GATE SPEED JJ size f0 asynch ckt f clocked ckt f (kA/cm2 ) (µm) (GHz) (GHz) (GHz) 1 2 4 8 20 50 100 3.5 2.5 1.75 1.25 0.8 0.5 0.35 125 170 230 315 470 700 940 52-78 71-107 97-146 132-198 197-296 293-440 394-592 13-31 18-43 24-58 33-79 49-116 73-176 99-232
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97: The superconductive IC chip fabrica
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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