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Superconducting Technology Assessment - nitrd

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ISSUES AFFECTING RSFQ CIRCUITS<br />

Margins and Bit-Error-Rates<br />

Any successful digital circuit technology requires large margins and low bit-error-rates (BER). Margins are the<br />

acceptable variation for which the circuit performs as designed. BER is the error-incidence per device per operation.<br />

Achieving high margins at high speed in RSFQ circuit technology depends critically on the symbiotic marriage<br />

of circuit design and chip fabrication. Margins and, consequently, BER in superconductors are affected by many<br />

factors, including all parameter spreads and targeting, noise, gate design, power (current) distribution cross-talk,<br />

signal distribution cross-talk, ground plane return currents, moats and flux trapping, and timing jitter.<br />

Bit Error Rate and Integration Scale<br />

It is necessary to balance performance and manufacturing issues. IC values fall in the range 0.1-0.2 mA, to ensure<br />

adequate noise immunity while keeping the total current and power dissipation as small as possible. A high J C value<br />

improves speed, but requires smaller junction size, so parameter spreads may be more difficult to control.<br />

Characteristic parameter spreads must be many times smaller than the operating margins of the circuits in order<br />

to achieve VLSI densities. The requirements for petaflops computing are especially restrictive in that a very low BER<br />

is required. If one assumes one error per year is acceptable, then a 64 bit processor with 100 gates/bit, capable of<br />

petaflops throughput, would require a BER ~ 10 -26 . This BER can be used to quantify the requirements for foundry<br />

IC process control.<br />

BER<br />

0.5<br />

1e-20<br />

1e-26<br />

-------------------------------------------------------------------------------------------------------------------------------------<br />

1e-52<br />

0.7 0.9 1 1.1 1.3<br />

Effective Margin<br />

Figure 1. Calculated BER of a 2-JJ comparator as a function of operating margin, for IC =0.2 mA (lower curve), and IC =0.1 mA (upper curve).<br />

Horizontal line is for 10-26 BER, which is corresponds to one error/year for petaflops capacity<br />

169

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