Superconducting Technology Assessment - nitrd

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Univ. of Colorado Univ. of Texas at Austin Univ. of California at Santa Barbara TABLE 5-2. ACADEMIC ACTIVITY 5.1.2 OPTICAL INTERCONNECT TECHNOLOGY – READINESS Plan to build an array of 40 Gbps directly modulated VCSELs; has already achieved 10 Gbps and expect to reach 20 Gbps in the near future. Working on amplifierless receivers crucial for 4 K applications. Working on amplifierless receivers crucial for 4 K applications. All of these efforts are aimed at achieving devices and systems that will be practical for use in the near future in terms of cost and power consumption as well as performance. Although optical interconnects have been introduced in large-scale systems, some technical issues must be resolved for the use of optical interconnects in a superconducting computer: ■ The cryogenic operation of optical components must be determined; all the current development efforts are aimed at room temperature use with only minimal R&D effort for use at cryogenic temperatures. There do not appear to be any fundamental issues which would preclude the necessary developments. ■ Even with cryogenic operation, some optical components may dissipate too much power at the required data rates to be useful in a petaflops-scale system. However, Figure 5.2 shows that low power is achievable at significant data rates for many optical components. Figure 5-2. Four channel transceiver arrays operating at 10 Gbps/channel produced by IBM/Agilent. Total power consumption for 4 channels is less than 3 mW/Gbps. 101
5.1.3 OPTICAL INTERCONNECT TECHNOLOGY – PROJECTIONS The availability of optical components and their features is given in Table 5-3. 102 TABLE 5-3. PROJECTIONS FOR ELECTRO-OPTICAL COMPONENTS FOR RSFQ I/O CURRENT STATUS 2005 VCSEL Based CWDM Interconnect Systems: 12x4λ @ 300K DARPA Terabus LIGHT SOURCES DEVICE 50 Gbps VCSEL Arrays Frequency Comb Lasers OPTICAL MODULATORS VCSEL used as DWDM modulator Low Voltage Amplitude Modulator @ 40 K Exotic Modulator Materials: Organic Glass/Polymer/Magneto-Optic OPTICAL RECEIVERS Amplifierless Receivers matched to superconductors 25/50 Gbps Receiver Arrays @ 300K ELECTRONIC DEVICES Low Power, 50 Gbps Amplifier/Driver Arrays @ 40 K PASSIVE COMPONENTS Cryogenic Electrical Ribbon Cables at 25/50 Gbps Optical Ribbon Cables @ 4 K, 40 K Optical WDM Components @ 4 K, 40 K 12 x 4λ x 10 Gbps 10 Gbps 32λ x 1550 nm 2.5 Gbps 4-6 volts On-Off/ 40 Gbps Single Devices/ COTS Materials studies show 3x improvement over conventional materials 20 Gbps demonstrated 50 Gbps Single Devices – COTS 4 x 40 Gbps arrays Lab Single Amplifiers (InP-HEMT) – COTS 3 Gbps COTS meet Commercial Specs/ Fibers OK at 4 K COTS meet Commercial Specs DESIRED STATE 2010 8x8λ x 50 Gbps 50 Gbps 64λ x 980 nm 50 Gbps 0.5 volt on-off/ 50 Gbps Arrays 6-10 fold improvement in devices 50 Gbps Array Ideally, word-wide arrays Lower power, ideally, word-wide arrays 25/50 Gbps Cables at 4 K 4 K Operation CRYOGENIC USE TESTED N Y N/A N N N N N/A Y Y N N ONGOING R&D Y Y N Y Y Y N N N N N N
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113: For further discussions of the opti
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ Construct a detailed supercondu
Page 151 and 152: Appendix B
Page 153 and 154: 140 George Cotter Nancy Welker Doc
Page 155 and 156: Appendix C
Page 157 and 158: 144 TERMS/DEFINITIONS IHEC Integrat
Page 159 and 160: Appendix D
Page 161 and 162: The time-dependent behavior of this
Page 163 and 164: RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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