Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
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■ Superconductor processors will use a partitioned microarchitecture, where processing<br />
occurs in close proximity to data.<br />
■ In order to achieve high sustained performance, aggressive architectural techniques<br />
will be used to deal with memory access latency.<br />
Processors and Memory<br />
The capability in 2010 should be >1 million JJs per cm 2 , implying >100,000<br />
gates per cm 2 with clock speed >50 GHz.<br />
—————<br />
The technology should be brought to the point where an ASIC logic designer<br />
will be able to design RSFQ chips without being expert in superconductivity.<br />
—————<br />
An advanced 90 nm VLSI process after 2010 should achieve<br />
~ 250 million JJ/cm 2 and circuit speeds ~ 250 GHz.<br />
—————<br />
Three attractive memory candidates are at different stages of maturity:<br />
– Hybrid JJ-CMOS memory.<br />
– Single-flux-quantum superconducting memory.<br />
– <strong>Superconducting</strong>-magnetoresistive RAM (MRAM).<br />
—————<br />
A complete suite of CAD tools can be developed based primarily on corresponding<br />
tools for semiconductors.<br />
—————<br />
Total investment over five-year period: $119 million.<br />
Processors<br />
The complexity of RSFQ logic chips developed to date has been constrained by production facility limitations and<br />
inadequate design tools for VLSI. Although all demonstrated digital chips have been fabricated in an R&D environment<br />
with processing tools more than a decade older than CMOS, impressive progress has been made. The panel<br />
concludes that, given the design and fabrication tools available to silicon technology, RSFQ circuit technology can<br />
be made sufficiently mature by 2010 to support development of high-end computers.<br />
Ready for Investment<br />
The panel concluded that with the availability of a stable VLSI chip production capability, RSFQ processor technology<br />
will be ready for a major investment to acquire a mature technology that can be used to produce petaflops-class<br />
computers starting in 2010. (“Mature technology” means that a competent ASIC digital designer with no background<br />
in superconductor electronics would be able to design high-performance processor units.) This judgment<br />
is based on an evaluation of progress made in the last decade and expected benefits of an advanced VLSI process<br />
in a manufacturing environment. Although RSFQ circuits are today relatively immature, their similarity in function,<br />
design, and fabrication to semiconductor circuits permits realistic extrapolations.<br />
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