Superconducting Technology Assessment - nitrd

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3.1.2 RSFQ PROCESSORS – READINESS FOR MAJOR INVESTMENT Processor The panel believes that RSFQ processor technology is ready for a major investment to produce a mature technology that can be used to produce petaflops-class computers starting in 2010. “Mature processor technology,” means one that would enable a competent ASIC digital designer, with no background in superconductive electronics, to design high-performance processor units. This judgment is based on an evaluation of progress made in the last decade and projection of manufacturing environments, coupled with a roadmap for RSFQ circuit development coordinated with VLSI manufacturing and packaging technologies. Although large RSFQ circuits are relatively immature today, their similarity in function, design, and fabrication to semiconductor circuits permits realistic extrapolations. Most of the tools for design, test, and fabrication will continue to be derived from the semiconductor industry, but will need to be adapted for application in RSFQ design. Because of this, investment in this effort will not need to match that needed for semiconductor development. The Flux project at Northrop Grumman, Stony Brook, and JPL illustrates how progress in fabrication and circuit technology can be accelerated in tandem. In the three years from 2000 to 2003, fabrication technology was advanced by two generations, with gate libraries fully developed for each generation, and by early 2004 Northrop Grumman was ready to move to a 20 kA/cm 2 process. This was accomplished on a limited budget. The Flux-1 microprocessor, including scan path logic for testing, was designed and fabricated from a 10-cell library, and inter-chip communication circuits were designed and successfully tested up to 60 Gbps. Embedded Vector Registers, FIFO, and Small SFQ RAM Based on published reports, vector registers, FIFOs, and small SFQ RAM arrays are ready for the major investment needed to bring them to the required readiness for HEC. It will be necessary to: ■ Enlarge the memory size using an advanced fabrication process (Chapter 4). ■ Set up the read/write procedures to meet the needs of the processor. ■ Test the FIFO in a logic chip. Chip-side microstrip Following this, test circuits can be designed and fabricated for testing at 50 GHz. Once problems are resolved, a complete 64 x 64 FIFO register can be designed and fabricated for inclusion in a processor. S G G S G G Figure 3.1-3. Signal and ground pad geometry used on Flux-1. Pad size and spacing are 100 mm. Carrier-side microstrip 47
Inter-chip Communications Driver and receiver circuits have already been demonstrated to 60 Gbps per line in the NG fabrication processes. Since speed and bit error rate (BER) will improve as J C increases, the circuit technology is ready now. The principal task will be to accommodate the increased number of high-data-rate lines on each chip and MCM. Shrinking bump size and minimum spacing, better design tools, and simulation models will be important to minimize reflections and cross-talk at both the signal and ground chip-to-MCM bumps. The crossbar switch program provides a rich experience base in the engineering of ribbon cables. In particular, the trade-off between heat leak and signal loss is well understood. Table 3.1-2 summarizes the readiness of superconductive circuits today and projects readiness in 2010 based on the roadmap. In evaluating the circuit technology and projecting a high probability of success in HEC, the panel considered the availability of VLSI fabrication. As much as anything, success in RSFQ processor development will depend on a dedicated industrial-quality VLSI manufacturing facility that provides a significant step-up in topological design rules and chip yield from current R&D facilities (see Chapter 4). Cryogenic testing is much more difficult than room temperature testing. Testing at 50 to 100 GHz clock frequencies magnifies the challenge significantly. A high-speed test bench will be required that is customized to test and evaluate all superconductive circuits from the cell libraries through the RSFQ processor integrated with RAM, including memory and network switches. The test bench must provide environmental support (cooling, RF and magnetic shielding), power supplies, commercial and specialized digital test equipment, and fixturing to accommodate various device modules. SFQ diagnostic circuits have been demonstrated and should be employed to meet the requirements of the test plans. 48 TABLE 3.1-2. SUPERCONDUCTIVE CIRCUIT TECHNOLOGY READY FOR MAJOR INVESTMENT AND DEVELOPMENT Logic Circuit Type 2004 Readiness Projected 2010 Readiness SFQ RAM Hybrid RSFQ-CMOS RAM Monolithic RSFQ MRAM Vector Register, FIFO Communication Circuits I/O Switch – Small circuits @ lower speed. – Experimental 4 kb RAM @ low speed. – Analysis of SFQ ballistic RAM. – Experimental proof-of-concept. – RSFQ write/read concept formulated. – 32 bit FIFO @ 40 GHz. – Chip-to-chip @ 60 Gbps. – 10 Gbps driver. – 2.5 Gbps per port circuit switch, scalable. – >10 6 JJ/cm 2 @ 50 GHz clock. – 256 kb SFQ ballistic RAM @ 500 ps access time. – 256 kb hybrid @ 500 ps. – 128 kb hybrid @ 500 ps. – 4 kb FIFO @ 50 GHz. – 64-bit word-wide chip-to-chip @ 50 GHz. – 64-bit word-wide drivers @ 40 Gbps/s. – 64-bit word wide, scalable @ 50 Gbps per port.
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: Structurally, a high-end computer w
Page 29 and 30: 16 ■ Chalmers University in Swede
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: MCMs The design of MCMs for SCE chi
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: 4.6 ROADMAP AND FACILITIES STRATEGY
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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