Superconducting Technology Assessment - nitrd

Bias Currents
A major cause of degraded margins in large circuits is inductive coupling of bias currents to gate inductors. Bias
current increases approximately linearly with the number of JJs on a chip, at about 0.1 mA/JJ. For 10 3 junctions,
the total current required is ~ 100 mA, at 10 4 JJ, ~ 1 A, and at 10 6 JJ, 100 A. Even small currents can affect shifts
and reductions in margins in two ways: by direct inductive coupling to circuit inductors and by indirect coupling of
uncontrolled ground return currents. These effects have frequently been ignored for small circuits, where they are
small and are frequently compensated for by tweaking. By extension, they have frequently been neglected for large
circuits. From discussions at the 2004 Applied Superconductivity Conference digital circuits session (Hypres, ISTEC-SRL,
NG, and Chalmers), it appears that a major cause of degraded margins is due to bias currents.
- Direct coupling
Designers have implicitly assumed that mutual coupling between low impedance superconducting microstriplines
is negligible. However, as total bias currents have increased and metal line pitch has decreased, this assumption has
led to circuit failures. Northrop Grumman exhaustively tested several chips of a 4-bit slice of a MAC circuit (~ 1000
JJs) at low speed (ASC 2004). (Note that although testing was at low speed, all internal signals propagated at a
high speed of ~ 50 ps/stage). Margins in one particular path through the circuit were reduced to about +6%; for
other identical paths, they were comparable to design values of about +25%. Northrup Grumman was able to pinpoint
the problem since the only difference was the position of nearby bias lines in the low margin path. At 1-µm spacing,
the mutual inductance is > 8 x 10 -15 H/µm. Thus, 100 mA bias current coupling to a 10 µm line will produce
a flux of approximately four magnetic flux quanta. Northrup Grumman concluded that the bias current
shifted operating points and consequently reduced the margins.
The solution is to either place the bias lines far from circuit inductors or magnetically shield them. Accommodating
large spaces is contrary to achieving dense chips. Shielding more than doubles the separation. One favorable solution
is to locate current buses on separate layers, shielded from the active circuitry by a superconducting ground plane.
Subterranean power lines (under the ground plane) isolated from the circuits have been proposed by several groups
over the years; it has not yet been implemented in any process.
- Indirect coupling
A second method by which bias currents couple to gates is through return currents in the ground plane. It is
common practice for SFQ chips to be installed in a multi-lead probe with a common ground return for all leads.
One or more of these leads is used to supply the chip with power; others are used for input and output signals.
Even when two leads are assigned for power, in and out, the power supply generally shares a common ground
with other components. Return current distributes itself to all available ground leads to minimize the resistance.
The problem is that on-chip, ground current migrates by many paths to minimize the inductance. These currents
can couple into circuit inductors, shifting operating points, and consequently margins. This was conclusively
observed by Lincoln Laboratory during the NSA Xbar project. The return current is not (as is frequently assumed)
restricted to the ground plane either directly underneath the current lead, or to the edge of the chip. This effect
was observed at Northrop Grumman for a modest size chip and was circumvented by tweaking bias currents (both
positive and negative) down several lines until full circuit operation was achieved at speed. Of course, the latter
method is not a practical solution. The solution is to separate the power supply from all other grounds (a floating
supply) and place the bias + and – pins immediately adjacent to each other. In fact, one should make the bias supply
leads coaxial, coplanar, or at least twisted to minimize stray magnetic fields from large current leads coming to the
chip, and, use a coplanar or pseudo-coaxial pin arrangement. This was anticipated and implemented on FLUX-1.
Clocks, Jitter, and Timing
Clocks for SFQ circuits are themselves SFQ pulses, with similar power, pulse width, and jitter. Because high clock
frequencies are required and the speed of transmission in stripline or microstrip is ~ 1/3 the speed of light in
vacuum, clock signals cannot be supplied to an array of gates as they are in much slower CMOS circuits. Instead,
they must be transmitted and distributed in a manner similar to data signals. Clock signals are best-generated
on-chip using low-jitter circuitry, which have been demonstrated. Clock jitter and skew will be minimized if clock
signals are generated on-chip, distributed on-chip, and distributed between chips similar to SFQ data transfer
between chips.
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