Superconducting Technology Assessment - nitrd

2-4 layers 4-16 layers �
16 - 1000 layers
- Stacked packages
- Stack die
- Stacked die at wafer level
- SOI or multilevel crystallization
Stacked packages
Edge or through die interonnects
Thin die
Figure 6-4. Categorization of 3D packaging approaches.
Superconducting electronic circuits based on NbN and Nb Josephson junctions (JJs) were inserted in stack layers
and operated at temperatures as low as 4 K, indicating the flexibility and reliability of the material system used in
3-D chip stacks. Stacked systems were operated at 20 GHz. When the material selection and system design are
judiciously performed, chip stacks have been shown to operate reliably with mean time to failure exceeding 10
years, in a wide temperature range from – 270 C to 165 C and in hostile environments subjected to 20,000 G.
3-D packaging provides an excellent alternative to satisfy the needs of the high functionality system and sub-system
integration applications and can yield system architectures that cannot be realized otherwise.
When the power budget increases, thermal management layers can be inserted in the stack as alternating layers
in addition to active layers. Experimental and analytical results indicated that up to 80W can be dissipated in a stack
volume of 1cm 3 . Thermal resistance within the stack can be as low as 0.1 C/W.
6.2.2 3-D PACKAGING – READINESS
INCREASING NUMBER OF LAYERS
- Stacked packages
- System - in - stack (discretes)
- Stacked bare or modified die
- High speed stacks
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- Stacked bare or
modified die
- Thinner layers
- Stacking of die or multiple die
INCREASING PRODUCTION VOLUME
The design of 3-D packaged systems is technically feasible and fairly well understood. However, the design for larger
applications and high-speed operation above 10 GHz have not been completely investigated.
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