Superconducting Technology Assessment - nitrd

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3.3 THE 4K-INTERMEDIATE TEMPERATURE ELECTRICAL OPTION Since placing some optical components at 4K does not appear to be feasible, other approaches must be considered. The design of the cryogenics appears to be compatible with having a short (
3.4 COARSE VS. DENSE WAVE DIVISION MULTIPLEXING (CWDM VS. DWDM) The use of WDM for optical interconnects has been suggested by a number of authors, and demonstrated recently by Agilent under the DARPA Terabus program. This effort uses 4 wavelengths of Coarse WDM at 30 nm (5.5 THz) spacing from 990 to 1080 nm. The optical multiplexing components used here are compatible with the use of multimode fiber, which is highly advantageous for a system with a large fiber count from the standpoints of light collection efficiency and ease of alignment. However, it should be pointed out here that this may not be compatible with 50 Gbps operation, where the detector size may become smaller than the multimode fiber core size, entailing large optical coupling losses. This must be evaluated in a complete system design study. To achieve 64 channels (a word width) on a single fiber would require the use of the closer wavelength spacings, more typical of the standard Dense WDM spacing of 0.8 nm (100 GHz at 1550 nm). In this case it can be anticipated that single mode fiber and optical multiplexing components would be required, with the associated losses and tighter alignment tolerances. However, only a single fiber would be required for a word width, a considerable advantage for a large system. In addition, the use of single mode fibers would enable the use of Differential Phase Shift Keyed (DPSK) modulation, at least for the Intermediate Temperature to 300K link. This could lead to simpler modulators and improved performance. Another issue involved in the choice between CWDM and DWDM is that of manufacturability. This is more easily achieved in CWDM, where say 4 arrays (each array at a different wavelength) of 16 lasers each can be placed side by side to achieve 64 channels, than for DWDM where an array of 64 VCSELS with each laser operating at a different wavelength is required. A conservative data transmission concept using CWDM operating at half clock rate (25 Gbps) is illustrated in Figure 4. Given the successful achievement of the DARPA TERABUS goals by 2007 this technology should be commercially available by 2010. Figure 4: A 64-fiber, 4-wavelength, 25-Gbps CWDM System for bidirectional transmission totaling 6.4 Tbps between a superconductive processor at 4 K and high speed mass memory at 300K. Optical connections are shown in red, electrical in black. This technology should be commercially available by 2010. 220 DETECTOR ARRAY OUTPUT LINE DRIVERS DEMU 4λ DEMUX ELECTRICAL RIBBON CABLE DATA TRANSMISSION CONCEPT 4K CPU 40K 32 X 4λ x 25 Gbps 128 x 25 Gbps 4λ MUX 300K CPU 128 x 25 4 WAVELENGTH VCSEL ARRAY @ 25 Gbps 32 X 4λ x 25 Gbps 4λ MUX 128 x 25 Gbps 4λ DEMUX 4 K 40 K 300 K 4 WAVELENGTH VCSEL ARRAY @ 25 Gbps FROM MEMORY DETECTOR ARRAY TO MEMORY
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
Page 181 and 182: Appendix G
Page 183 and 184: The two-junction comparator, the ba
Page 185 and 186: Bias Currents A major cause of degr
Page 187 and 188: Power and bias current Power is dis
Page 189 and 190: Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 0.08 0.06 0.04 0.02 30 40 50 60 70
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Fig. 4. Junction fabrication proces
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: Fig. 11. Ground plane planarization
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: Fig. 17. Photograph of the FLUX-1r1
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
Page 215 and 216: Appendix J
Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
Page 223 and 224: Fig. 8. Layout-versus-Schematic ver
Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231: If technology, power, or cost limit
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
Page 239 and 240: Appendix L
Page 241 and 242: The bandwidth, chip density and int
Page 243 and 244: While using short flex cables is th
Page 245 and 246: We must note that the reparability
Page 247 and 248: Figure 7. A typical cryocooler encl
Page 249 and 250: Small Cryocoolers Among commercial
Page 251 and 252: Although cooling of the 4 K circuit
Page 253 and 254: Supplying DC current to all of the
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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