Superconducting Technology Assessment - nitrd

The microarchitecture of superconductor processors must support a truly localized computation model in order
to have processor functional units fed with data from registers located in very close proximity to the units. Such
organization makes distributed, multi-bank register structures much more suited for superconductor processors
than the monolithic multi-ported register files used in CMOS microprocessors. An example of such a partitioned
architecture for integer processing was developed for the 20 GHz FLUX-1 microprocessor, which could be called
processing-in-registers.
2.4.4 MEMORY HIERARCHY FOR SUPERCONDUCTOR
PROCESSORS AND SYSTEMS
Efficient memory hierarchy design including capacity, latency, and bandwidth for each of its levels is one of
the most important architectural issues. Some memory issues have been addressed in simulation and low-speed
experiments, but there are only analytical results for multi-technology memory hierarchy for a petaflops system
with superconductor processors.
The principal design issues are:
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■ Technology choices for each level of memory hierarchy.
■ Interfacing between different memory levels.
■ Latency avoidance/tolerance mechanisms in the processor microarchitecture.
Currently, there are several technologies that should be studied as potential candidates for inclusion into such a memory hierarchy:
■ RSFQ.
■ JJ-CMOS.
■ SFQ-MRAM.
■ Semiconductor SRAM and DRAM (at higher temperatures, outside the cryostat).
RSFQ Memory
■ Traditionally-designed RSFQ RAM (e.g., the FLUX-1 instruction memory) rely on point-to-point
implementation of the bit and word lines with tree structures containing RSFQ asynchronous
elements such as splitters and mergers at each node of these trees. Such design has a very negative
effect on both density and latency.
■ Currently, the fastest type of purely RSFQ memory is a first-in-first-out (FIFO)-type, shift
register memory, which has demonstrated high-speed (more than 50 GHz), good density,
and low latency at the expense of random access capabilities. This type of memory can
be efficiently used to implement vector registers, which makes vector/streaming architectures
natural candidates for consideration for superconductor processors.
JJ-CMOS Memory
■ The closest to RSFQ memory in terms of speed, but much higher in density, is hybrid JJ-CMOS
memory, for which simulation results show latencies of few hundred picoseconds for 64 kbit
memory chips. A 50 GHz processor with a reasonably large off-chip hybrid JJ-CMOS memory
on the same MCM will need architectural mechanisms capable of tolerating 30-40 cycle
memory access latencies.