Superconducting Technology Assessment - nitrd

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The extensive modeling of defect density and its effect on die yield developed for the semiconductor industry is directly applicable to superconductive IC chip manufacture because the fabrication processes are similar. Understanding and predicting yield will be important, because it will have a strong bearing on sizing the resources needed to produce a petaflops-scale computer. Defect density determines practical IC chip size. A typical estimate for present defect density in a clean superconductor foundry is 1-2 defects/cm 2 . Defect density on the order of 0.1 defect/cm 2 will be needed to produce 2 x 2 cm 2 chips with yields greater than 50%. The optimal IC chip size is a tradeoff between IC chip yield and packaging complexity. The use of Class 1 and 10 facilities and low-particle tools, and good discipline by personnel is required to reduce the process-induced and environment-induced defects to this level. 4.5.5 IC CHIP MANUFACTURE – PRODUCTION OF KNOWN GOOD DIE Integrated circuit manufacture may be defined as the production of known good die. Producing known good die will depend on the overall circuit yield, which is the product of the individual yields of all the processes used to produce and test the IC chips. For a large-scale system, the number of IC chips required is large (~40,000) and the yield may be low, at least initially. A large volume of wafers will have to be fabricated and tested. Wafer-level, high-speed cryogenic (4 Kelvin) probe stations will be required in order to screen die before dicing. Built-in self-test (BIST) will certainly simplify the screening process. Tradeoffs between the quality of and overhead imposed by BIST should be considered early in the design cycle. Sophisticated BIST techniques have been developed in the semiconductor industry and are readily applied to SCE chips. Simple BIST techniques have already been used to demonstrate high-speed circuit operation on-chip, using a low-speed external interface. High-speed probe stations and BIST techniques will not be available in the early stages of development. Screening for chips likely to be functional will be limited to low temperature screening of wafers via Process Control Monitor chips and room temperature electrical probing and visual inspection. For a large-scale system, the number of IC chips required is large (~40,000), and the yield may be low, at least initially. Experience has shown that IC chip yield in high-volume silicon foundries is low during the initial or pre-production phase, increases rapidly as production increases, and then levels off at product maturity. Due to the volume of IC chips for the petaflops computing, the superconductor foundry will probably operate on the boundary between pre-production and early production phases. Production-type tools will be needed to produce the required volume of IC chips, and larger wafers will be needed to produce the IC chips in a cost-effective and timely way when the number of IC chips is large and the yield is relatively low. The panel projects that 200 mm wafers will be adequate. Table 4-9 shows case examples of throughput requirements for various yield values, assuming a 24-month production run after an initial development phase to reach 5% yield. As shown, the worst case scenario shows the facility must be sized to produce 1,000 wafers per month. As the product matures, the panel expects to reach well above 20% yield, which will comfortably satisfy the production volume needs. Minimizing the number of different IC chip types (e.g., memory vs. processor) will also reduce the total number of wafers needed. 89
4.6 ROADMAP AND FACILITIES STRATEGY 4.6.1 ROADMAP AND FACILITIES STRATEGY – ROADMAP The roadmap to an SCE IC chip manufacturing capability must be constructed to meet the following criteria: ■ Earliest possible availability of IC chips for micro-architecture, CAD, and circuit design development efforts. These IC chips must be fabricated in a process sufficiently advanced to have reliable legacy to the final manufacturing process. ■ Firm demonstration of yield and manufacturing technology that can support the volume and cost targets for delivery of functional chips for all superconductive IC chip types comprising a petascale system. ■ Support for delivery of ancillary superconductive thin film technologies such as flip-chip bonding, MCM's, and board-level packaging for technology demonstrations. ■ Availability of foundry services to the superconductive R&D community, and ultimately for other commercial applications in telecommunications, instrumentations, and other applications. From these broad criteria, a few “rules of the roadmap” can be derived. First, rapid establishment of an advanced process with minimal development is desirable. Examples of pilot and R&D level processes of this type are the NGST 20 kA/cm 2 process and the NEC 10 kA/cm 2 process. However, such an early process is not expected to be sufficient to meet all the needs of a petaflops-scale system, so development and process upgrades must be planned as well. Early establishment of such a pilot process will not allow rigorous establishment of manufacturing facilities, equipment, and processes, so this must also be planned in separately. In a more relaxed scenario, establishment of a manufacturing capability could be in series with the pilot capability, but the relatively short five-year time frame contemplated does not allow this. In order to assure the most cost effective in introduction of manufacturing capability, use of the Intel “Copy Exactly” process development method should be adopted to the greatest extent possible. A second possibility is development and establishment of capability at multiple sites or sources. Unfortunately, the development of each generation of process at different sites—perhaps from different sources—does not allow implementation of any form of the Intel “Copy Exactly” philosophy and greatly increases the cost and schedule risk for the final manufacturing process. 90 IC chip total Wafer total Wafer starts per month Chip tests/month @ 4K TABLE 4-9. SCALING REQUIREMENTS FOR SCE IC CHIP PRODUCTION Yield = 5% 10% 20% 30% 737,280 23,040 960 30,720 368,640 11,520 480 15,360 184,320 5,760 240 7,680 122,880 3,840 160 5,120
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: Circuits/ Organizations Flux-1/ NG,
Page 60 and 61: 3.1.2 RSFQ PROCESSORS - READINESS F
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101: Parameter spreads in superconductiv
Page 105 and 106: Figure 4-6. Timeline for developmen
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: 98 Data Communication Requirement R
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: 6.2. 3-D PACKAGING Conventional ele
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ Construct a detailed supercondu
Page 151 and 152: Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Fig. 4. Junction fabrication proces
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Table 6 Junction Array Summary of T
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Fig. 11. Ground plane planarization
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B. Yield Yield measurements are an
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Fig. 17. Photograph of the FLUX-1r1
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Figure 7. A typical cryocooler encl
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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