Superconducting Technology Assessment - nitrd

PROCESSOR
MEMORY L1
MEMORY L2
MEMORY L3
MEMORY L4
Figure 5-3. The use of crossbar switching in supercomputers.
CROSSBAR SWITCHING NETWORK
5.4.1 DATA ROUTING: 4 K RSFQ TO 4 K RSFQ – STATUS
PROCESSOR
MEMORY L1
MEMORY L2
MEMORY L3
MEMORY L4
Electronic technology continues to make huge strides in realizing high-speed signaling and switching. Data rates
of 10 Gbps have been realized on electronic serial transmission lines for distances in the order of tens of centimeters
on printed circuits boards and as long as 5 meters on shielded differential cables. Application-specific integrated
circuits (ASIC) with increasing speed and decreasing die area, used as switching fabrics, memory elements, and
arbitration and scheduling managers, have shown increasing performance over a long period of time.
Issues such as power, chip count, pin count, packaging density, and transmission line limitations present a growing
challenge to the design of high-rate semiconductor-based electronic switches. Next-generation semiconductor
processes, along with increased device parallelism and implementation of multistage architectures, can increase the
total switching capacity of a multistage semiconductor-based electronic switch to a 128 x 128 matrix of 50 Gbps
ports. Progress beyond such switches is expected to be slow, as evidenced in the recent International Technology
Roadmap for Semiconductors (ITRS) report.
Alternatively, superconductivity is an ideal technology for large-scale switches. Ideal transmission lines, compact
assemblies, and extremely low gate latency permit operation with low data skew (hence permitting low overhead
transmission of word-wide parallel data for extremely high throughput). The superconductive implementation of
the crossbar architecture permits large switches, operating in single-cast or broadcast mode.
Components of a 128x128 superconductive scalable crossbar switch have been demonstrated at NGST
(Figure 5-4), using voltage state superconductive switch elements. The switch chips were inserted onto an MCM
along with amplifier chips, and data transmission up to 4.6 Gbps was observed. Latencies were in the order of
2-5 ns. Simulations indicated that this type of switch could be operated at >10 Gbps, but 50 Gb/s require RSFQ
switch elements. The crucial component for viable RSFQ switches at 20-50 Gbps is cryogenic amplification without
high power penalties.
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