Superconducting Technology Assessment - nitrd

This chapter:
■ Reports the status of superconductive RSFQ processor and cryogenic RAM technology.
■ Projects the capability that can be achieved in 2010 and beyond with adequate
investment.
■ Estimates the investment required to develop RSFQ processors and cryogenic memory
for high-end computing (HEC) engines by 2010.
The Hybrid Technology Multi-thread (HTMT) architecture study projected that petaflops performance can be
achieved with 4,096 RSFQ processors operating at a clock frequency of 50 GHz and packaged in approximately
one cubic meter. Each processor may require 10 million Josephson junctions (JJs). To achieve that goal,
RSFQ chip technology must be matured from its present state to >1 million JJs per square centimeter with clock
frequencies >50 GHz.
The panel categorizes chips required for HEC into four classes that must be compatible in speed, bandwidth, and signal levels:
■ Processor.
■ Memory.
■ Network.
■ Wideband input/output (I/O) and communications.
Although these circuits are based on a common device foundation, they are unique and have different levels of maturity.
To provide low latency, a large, fast-access cryogenic RAM is required close to the processors. Since very large bandwidth
interconnect is a requirement for HEC, wideband interconnects are also needed at all levels of communications. To
achieve these goals, microarchitecture, circuit design, and chip manufacturing need to be improved in synchrony.
This chapter is divided into three sections:
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■ Section 3.1 reviews the status, readiness for major investment, roadmap and
associated investment, major issues for RSFQ processors, and future projections.
■ Section 3.2 reviews the status, readiness for major investment, roadmap and
associated investment, major issues for cryogenic RAM, and future projections.
■ Section 3.3 elaborates on CAD tools and design methodology required for
successful design of large RSFQ circuits.