Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
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SFQ RAM Status<br />
The results of five completely superconductive RAM projects are summarized in Table 3.2-4.<br />
ISTEC-SRL<br />
Northrop<br />
Grumman<br />
HYPRES<br />
Stony Brook<br />
University<br />
Northrop<br />
Grumman<br />
TABLE 3.2-4. SUPERCONDUCTIVE RAM PROJECTS<br />
Organizations Project Parameter Comments<br />
– RSFQ decoder activates<br />
latching drivers, which<br />
address SFQ memory cells.<br />
– VT cells.<br />
– RSFQ input/output.<br />
– NEC VT cells.<br />
– Latching driver impedance<br />
matched to word<br />
transmission line for BW.<br />
– CRAM.<br />
– Pipelined DC powered<br />
SFQ RAM.<br />
– RAM with SFQ access.<br />
– Ballistic RAM (BRAM).<br />
– Cells are 1-JJ, 1-inductor.<br />
– SFQ pulses not converted<br />
to voltage-state drive levels.<br />
– 256 bits.<br />
– 3747 JJ.<br />
– 1.67 mW@ 10kHz.<br />
– 2.05mmx1.87mm.<br />
– Speed > 1 GHz expected,<br />
limited by TOF.<br />
– 16 kb on 1-cm2 chip in<br />
2 kA/cm2 process.<br />
– Incomplete.<br />
– Long junctions used.<br />
– 400ps access, 100ps cycle<br />
time estimated.<br />
– 16 kb on 1-cm2 .<br />
– Power estimated @ 8 mW<br />
for 16 kb.<br />
– Read pulse travels on active<br />
line of JTL/cell stages.<br />
– SFQ pulses propagate through<br />
bit lines and are directly detected<br />
at end of bit line.<br />
– Bit lines are controlled impedance<br />
passive transmission lines.<br />
– Waveform generated on word<br />
line couples ~50mA to each<br />
cell in row.<br />
– Planned 16 kb of 64 blocks<br />
on 2.5cm2 .<br />
– 107 mW for 16 kb.<br />
– SRL 4.5 kA/cm2 process.<br />
– Discontinued.<br />
– Decoder tested @ 0.5 GHz.<br />
– 1 kb RAM with address.<br />
line and sense amplifiers<br />
partially tested.<br />
– 6 x 6 array tested at low speed,<br />
1-cell @0.5 GHz.<br />
– 16 kb design used<br />
4 4kb subarrays.<br />
– 4 kb block tested at low speed.<br />
– Due to block pipeline, time<br />
for 64-kb RAM scales as: 600ps<br />
access, ~100ps cycle time.<br />
– Density increase, cycle time<br />
reduced to 30ps, access time<br />
~400ps projected with 20kA/cm2 .<br />
– Discontinued at end<br />
of HTMT project.<br />
– Developed SFQ cell and decoder<br />
for 1kb RAM.<br />
– Problem is strong content<br />
dependence affected operation.<br />
– Simulated SFQ signals passed<br />
through series of 64 cells in<br />
~50ps to simulate read.<br />
– Decoder delay estimated at 40ps.<br />
– DRO cells so refresh must<br />
be accommodated.<br />
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