Superconducting Technology Assessment - nitrd

Issues and Concerns
Present simulation, layout, and verification tools could form the foundation of a new CAD capability. Translating
existing CAD capability, DRC, LVS, and generation of Pcells for physical layout, to a new foundry process or processes
should be quick and relatively easy. Additional CAD development should be driven by advances in feature size,
signal frequency, integration scale, and circuit complexity, all of which need to leapfrog present capability by
several generations.
Physical models
A mature RSFQ technology will operate closer to ultimate physical limits than present technology. Ultimately, this
will require new models of junctions, quantum noise, transmission lines, and inductors for physical simulation.
Points for consideration include:
■ JJs. The present RSJ model may not be adequate for sub-micron, high J C junctions.
■ Quantum noise. Quantum noise may add significantly to thermal noise in high J C junctions.
■ Transmission lines. These are presently considered dispersion- and attenuation-free,
which may not be adequate for signals with frequency content approaching the Nb gap
frequency (about 800 GHz).
■ Inductors. Kinetic inductance becomes increasingly large relative to magnetic inductance
at sub-micron linewidths and may be frequency dependent at high frequency.
All of these effects should be manageable if they can be captured in physical simulation. Standard physical simulators
have already been extended to include superconductive elements such as JJs (e.g., WRSpice). Addition of new
elements may now be required.
Parameter extraction from physical layout is needed both for LVS and for back annotation, whereby a netlist is generated
from the physical layout. Verification is presently done without checking inductance values. Back annotation
presently can only be done at the gate level using LMeter. A true 3D EM (3-dimensional electromagnetic) algorithm
may be required to attain high accuracy at sub-micron sizes. Both the physical-level simulator and the inductance
extraction tools should be integrated into the existing CAD environment.
Hardware Description Language
VHDL simulation methods will also require further development. More sophisticated modeling will be required for
complex, random logic circuits. Standard delay format could be readily implemented in the usual way, but it is not
clear whether this would be effective in superconductive circuits. Also at issue are the effects of signal jitter and of
timing-induced probabilistic switching in RSFQ gates. These may combine to make effective hold and setup times
in the low BER regime significantly larger than idealized, noiseless circuit simulation would indicate. While the
mathematical formalism is well understood, it has not been implemented in CAD for automated checking.
Board design and packaging design could proceed using standard 3D EM software (e.g., HFSS) and standard methods,
in which models generated in the frequency domain are translated to the time domain for use in physical-level
simulations. Software development may be required because the frequency range of interest extends up to 1 THz,
and EM modeling must be able to handle superconductors. This will require modification and extension of the
commercial software package.
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