Superconducting Technology Assessment - nitrd

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■ Chalmers University in Sweden is developing RSFQ technology to reduce error rates in CDMA
cell phone base stations.
■ Academic research continues at the Jet Propulsion Laboratory and the Universities
of California, Berkeley and Stony Brook. Among government agencies, NIST (Boulder),
NSA, and ONR have resident expertise.
Some additional companies are working in analog or power applications of superconductivity, but they are not
involved in digital devices.
1.8 CONTENTS OF STUDY
The panel organized its deliberations, findings, and conclusions into five topical areas, with each chapter going into
detail on one of the following:
■ Architectural considerations.
■ Processors and memory.
■ Superconductor chip manufacturing.
■ Interconnect and input/output.
■ System integration.
(The attached CD contains the full text of the entire report and all appendices.)
1.9 CHAPTER SUMMARIES
Architectural Considerations
No radical execution paradigm shift is required for superconductor processors,
but several architectural and design challenges need to be addressed.
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By 2010 architectural solutions for 50-100 GHz superconductor processors
with local memory should be available.
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Total investment over five-year period: $20 million.
RSFQ logic at high clock rates introduces unique architectural challenges. Specifically:
■ The on-chip, gate-to-gate communication delays in 50 GHz microprocessors
will limit the chip area reachable in one cycle to less than 2 mm.
■ One can no longer employ clock or data buses.
■ Local clocks will have to be resynchronized both on-chip and between chips.