Superconducting Technology Assessment - nitrd

Table 6
Junction Array Summary of Three NGST Process Generations
IV. PROCESS INTEGRATION
A. Design Rules
Design rules provide details on circuit layout, minimum
feature sizes, and electrical rules for the processes and
are available from many institutions listed in Table 1. The
importance of the design rule document is that it describes
the process capability and provides the range of parameters
expected on any given chip, given adherence to the
guidelines specified. The NGST 8-kA/cm niobium foundry
process has demonstrated functional circuit yield at a level
of integration of 2000–3000 junctions per chip and clock
speeds of 300 GHz. The near-term goal was to yield circuits
with greater than 60 000 junctions per chip utilizing existing
fabrication tools. To reach this goal requires a very stable
fabrication process, good CD control, predictable electrical
performance, highly optimized design rules, and low defect
density.
The NGST 8-kA/cm process has 14 masking steps,
which includes one ground plane, two resistor layers, and
three wiring layers [66]. The minimum wire pitch is 2.6 m,
and the minimum junction and contact sizes are 1.25 and
1.0 m, respectively. This process has demonstrated fabrication
of junctions as small as 1.0 m and wire pitch of 2.0 m,
but design rule minimum feature sizes were conservative to
guarantee a high yield. Minimum feature size design rules
are summarized in Table 3.
Design rules should be process-bias independent, i.e.,
drawn features are equal to final, on-wafer features. Process
bias is the loss (or gain) in feature size between drawn
and final on-wafer dimensions due to lithography and etch
processes. The process bias is compensated for by sizing the
reticle (mask). Reticle sizing for each layer is determined
from a combination of electrical, optical, and SEM measurements.
When process bias becomes a substantial fraction
of the minimum feature size, further reductions in design
rules are impossible even if the process tools are capable of
defining smaller features. Therefore, lithography and etch
processes should be optimized to produce minimum loss (or
gain) in CD.
B. CD Control
NGST used a photoresist optimized for both g-line and
i-line wavelengths [65]. Using this resist and g-line 1X Ultratech
steppers, a resolution of 0.65 m (light field reticle) was
achieved, and 1.0- m features could routinely be defined in
Fig. 9. SEM photograph showing the reentrant step coverage of
sputter-deposited SiO over a 500-nm metal step.
photoresist with minimum CD loss and excellent reticle linearity
[59]. This photoresist is more than adequate for the
8-kA/cm generation. Batch develop of the photoresist has
been the standard practice, but spray develop has the potential
to further reduce across-wafer CD variation and should
be become standard practice in the future.
All niobium layers, including junction and counterelectrodes,
are reactively ion etched in SF . This dry etch process
has been highly optimized to achieve an across-wafer (for
100-mm-diameter wafers) etch rate nonuniformity of less
than 1%. The RIE tool operates at 30-W RF power and
15-mtorr pressure. Under these conditions, the RIE process
produces little damage to the photoresist, and etched features
(junctions and wires) have vertical sidewalls. The CD loss
for the first and second wiring layers is less than 0.1 m and
between 0.1 and 0.2 m for the third thicker wiring layer.
Etch parameters for niobium and for other materials are
summarized in Table 5.
CD control of contacts in the SiO interlevel dielectric
layers is not as critical. The minimum contact feature is
1.0 m, and the contact etch must simply clear a 1.0- m
minimum opening. Contacts are etched in a mixture of
CHF %O to produce sloped walls and improve step
coverage.
C. Interlevel Dielectric
The most common interlevel dielectric material for
superconductor integrated circuit fabrication is sputter-deposited
SiO [68]–[70]. It has low defect density and
can be deposited at low temperatures, since temperatures
above about 150 C can degrade the electrical properties of
Nb/Al-AlO /Nb junctions. However, the step coverage of
sputter-deposited SiO is poor and would limit yield of an
LSI or VLSI circuit process [41], [68]. The cross section of
sputter-deposited SiO over a step is shown in Fig. 9 and
illustrates the “reentrant” structure that leads to poor step
coverage by the next metal layer. Step coverage improves
upon applying RF bias to the wafer during sputter deposition
[71]. RF bias produces positive ion bombardment of the
wafer surface and resputtering of the deposited oxide. The
1524 PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004