Superconducting Technology Assessment - nitrd

Table 4-1 summarizes the roadmap for chip production for aggressive government, moderate, and no
funding scenarios.
Potential exists for further improvement of the technology beyond 2010. That vision is summarized in Table 4-2.
The roadmap established by the panel, detailed in section 4.6, provides for the development of two new generations
of RSFQ chip technology by 2010 to be developed in a pilot line and then transferred to a manufacturing line. The
first generation process, which is projected for 2007, builds on the most advanced process demonstrated to
date, adding minimal improvements but using newer equipment based on 250 nm complementary metal oxide
semiconductors (CMOS) processing.
The second generation process, which is projected for 2009, assumes narrower line widths (with the same 250 nm
lithographic tools), a modest increase in critical current density, J c, and the introduction of well understood
planarization processes from CMOS.
Beyond 2010, a significantly denser, faster chip technology could be developed, but in a time frame, and requiring
resources, outside of the roadmap outlined in this study. This scenario assumes migration to 90 nm or better equipment
and processes, moving to layer counts comparable to future CMOS technology, and aggressively increasing the
current density to achieve junction speeds at the limit of Nb technology (1,000 GHz).
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Aggressive
Funding
Moderate
Funding
No Funding
TABLE 4-1. SCE INTEGRATED CIRCUIT CHIP MANUFACTURE ROADMAP
– Establishment of a modest volume manufacturing capability
and infrastructure for delivery of known good die.
– Clock rates of 50 GHz or higher, densities of 1-3 million JJs
per cm 2 by 2010. Yield and manufacturability established
and costs understood.
– Establishment of low volume pilot line/R&D capability with
some upgrades to present R&D capabilities.
– Pilot/R&D capability demonstrations of density and clock
rates of interest by 2014. Yield and manufacturability will
not be demonstrated.
– Continued R&D efforts in academic and foreign laboratories.
Low continuity of effort.
– Modest increases in clock rate and circuit densities
in R&D demonstrations. Performance, gate density,
and manufacturability inadequate for petaflops computing.
$125 M
~$60 M
0